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pmu: %s :: duplicate id
not supportedinvalid parameterspfmlib not initializedevent not foundinvalid or missing unit maskout of memoryinvalid event attributeinvalid event attribute valueattribute value already settoo many parametersparameter is too smallNo OS (raw PMU)??pfmlib_perf_event_pmu.ccpu/sys/bus/event_source/devices%s/%s/events/%sperf_events generic PMUperfslotstopdown-retiringtopdown-bad-spectopdown-fe-boundtopdown-be-boundPERF_COUNT_HW_CPU_CYCLESCPU-CYCLESPERF_COUNT_HW_INSTRUCTIONSCACHE-REFERENCESPERF_COUNT_HW_CACHE_MISSESCACHE-MISSESBRANCH-INSTRUCTIONSPERF_COUNT_HW_BRANCH_MISSESBRANCH-MISSESPERF_COUNT_HW_BUS_CYCLESBUS-CYCLESSTALLED-CYCLES-FRONTENDIDLE-CYCLES-FRONTENDSTALLED-CYCLES-BACKENDIDLE-CYCLES-BACKENDPERF_COUNT_HW_REF_CPU_CYCLESREF-CYCLESPERF_COUNT_SW_CPU_CLOCKCPU-CLOCKPERF_COUNT_SW_TASK_CLOCKTASK-CLOCKPERF_COUNT_SW_PAGE_FAULTSPAGE-FAULTSCONTEXT-SWITCHESPERF_COUNT_SW_CPU_MIGRATIONSCPU-MIGRATIONSPERF_COUNT_SW_PAGE_FAULTS_MINMINOR-FAULTSPERF_COUNT_SW_PAGE_FAULTS_MAJMAJOR-FAULTSPERF_COUNT_SW_CGROUP_SWITCHESCGROUP-SWITCHESPERF_COUNT_HW_CACHE_L1DL1 data cacheread accesswrite accessprefetch accesshit accessmiss accessL1-DCACHE-LOADSL1 cache load accessesL1-DCACHE-LOAD-MISSESL1 cache load missesL1-DCACHE-STORESL1 cache store accessesL1-DCACHE-STORE-MISSESL1 cache store missesL1-DCACHE-PREFETCHESL1 cache prefetch accessesL1-DCACHE-PREFETCH-MISSESL1 cache prefetch missesPERF_COUNT_HW_CACHE_L1IL1 instruction cacheL1-ICACHE-LOADSL1I cache load accessesL1-ICACHE-LOAD-MISSESL1I cache load missesL1-ICACHE-PREFETCHESL1I cache prefetch accessesL1-ICACHE-PREFETCH-MISSESL1I cache prefetch missesPERF_COUNT_HW_CACHE_LLLast level cacheLLC-LOADSLLC-LOAD-MISSESLast level cache load missesLLC-STORESLLC-STORE-MISSESLast level cache store missesLLC-PREFETCHESLLC-PREFETCH-MISSESPERF_COUNT_HW_CACHE_DTLBDTLB-LOADSData TLB load accessesDTLB-LOAD-MISSESData TLB load missesDTLB-STORESData TLB store accessesDTLB-STORE-MISSESData TLB store missesDTLB-PREFETCHESData TLB prefetch accessesDTLB-PREFETCH-MISSESData TLB prefetch missesPERF_COUNT_HW_CACHE_ITLBITLB-LOADSInstruction TLB load accessesITLB-LOAD-MISSESInstruction TLB load missesPERF_COUNT_HW_CACHE_BPUBranch Prediction UnitBRANCH-LOADSBranch  load accessesBRANCH-LOAD-MISSESBranch  load missesPERF_COUNT_HW_CACHE_NODENode memory accessNODE-LOADSNode  load accessesNODE-LOAD-MISSESNode  load missesNODE-STORESNode  store accessesNODE-STORE-MISSESNode  store missesNODE-PREFETCHESNode  prefetch accessesNODE-PREFETCH-MISSESNode  prefetch misses%s/%s/typepfmlib_perf_event.c:%s=%lu:%s=%dmgmhexclperf_event extendedperf_eventmonitor at user levelmonitor at kernel levelmonitor at hypervisor levelsampling periodfreqsampling frequency (Hz)preciseprecise event samplingexclusive accessmonitor guest executionmonitor host executionCPU to programpinnedpin event to countershw_smplenable hardware samplingr0000r%lxperf_events raw PMUperf_rawpfmlib_intel_x86_perf_event.c%s/%spfmlib_amd64_perf_event.c guest=%d host=%dAuthenticAMDpfmlib_amd64.c:0x%xpmu: %s missing attr_desc
monitor at priv level 0monitor at priv level 1, 2, 3edge levelcounter-mask in range [0-255]monitor in hypervisormeasure in guestIntel CoreUNHALTED_CORE_CYCLESINSTRUCTION_RETIREDUNHALTED_REFERENCE_CYCLESUnhalted reference cyclesLLC_REFERENCESLAST_LEVEL_CACHE_REFERENCESLLC_MISSESLAST_LEVEL_CACHE_MISSESBRANCH_INSTRUCTIONS_RETIREDBR_INST_RETIRED:ANYMISPREDICTED_BRANCH_RETIREDBR_INST_RETIRED_MISPREDRS_UOPS_DISPATCHED_CYCLESRS_UOPS_DISPATCHEDRS_UOPS_DISPATCHED_NONERS_UOPS_DISPATCHED:i=1:c=1LOAD_BLOCKLoads blockedSB_DRAIN_CYCLESSTORE_BLOCKCycles while store is waitingSEGMENT_REG_LOADSSSE_PRE_EXECDTLB_MISSESMEMORY_DISAMBIGUATIONMemory disambiguationPAGE_WALKSNumber of page-walks executedFP_COMP_OPS_EXEFP_ASSISTMultiply operations executedDivide operations executedCYCLES_DIV_BUSYCycles the divider is busyIDLE_DURING_DIVDELAYED_BYPASSDelayed bypassL2_ADSL2_DBUS_BUSY_RDL2_LINES_INL2_M_LINES_INL2 cache line modificationsL2_LINES_OUTL2 cache lines evictedL2_M_LINES_OUTL2_IFETCHL2_LDL2 cache readsL2_STL2 store requestsL2_LOCKL2 locked accessesL2_RQSTSL2_REJECT_BUSQRejected L2 cache requestsL2_NO_REQEIST_TRANSTHERMAL_TRIPNumber of thermal tripsCPU_CLK_UNHALTEDL1D_CACHE_LDL1 cacheable data readsL1D_CACHE_STL1 cacheable data writesL1D_CACHE_LOCKL1D_ALL_REFL1D_ALL_CACHE_REFL1D_REPLL1D_M_REPLL1D_M_EVICTL1D_PEND_MISSL1D_SPLITSSE_PRE_MISSLOAD_HIT_PREL1D_PREFETCHL1 data cache prefetchBUS_REQUEST_OUTSTANDINGBUS_BNR_DRVBUS_DRDY_CLOCKSBUS_LOCK_CLOCKSBUS_DATA_RCVBUS_TRANS_BRDBurst read bus transactionsBUS_TRANS_RFORFO bus transactionsBUS_TRANS_WBBUS_TRANS_IFETCHBUS_TRANS_INVALInvalidate bus transactionsBUS_TRANS_PWRPartial write bus transactionBUS_TRANS_PPartial bus transactionsBUS_TRANS_IOIO bus transactionsBUS_TRANS_DEFDeferred bus transactionsBUS_TRANS_BURSTBUS_TRANS_MEMMemory bus transactionsBUS_TRANS_ANYAll bus transactionsEXT_SNOOPExternal snoops responsesCMP_SNOOPBUS_HIT_DRVHIT signal assertedBUS_HITM_DRVHITM signal assertedBUSQ_EMPTYBus queue is emptySNOOP_STALL_DRVBus stalled for snoopsBUS_IO_WAITL1I_READSL1I_MISSESInstruction Fetch Unit missesITLB small page missesINST_QUEUECYCLES_L1I_MEM_STALLEDILD_STALLBR_INST_EXECBranch instructions executedBR_MISSP_EXECBR_BAC_MISSP_EXECBR_CND_EXECBR_CND_MISSP_EXECBR_IND_EXECBR_IND_MISSP_EXECBR_RET_EXECRET instructions executedBR_RET_MISSP_EXECBR_RET_BAC_MISSP_EXECBR_CALL_EXECCALL instructions executedBR_CALL_MISSP_EXECBR_IND_CALL_EXECBR_TKN_BUBBLE_1BR_TKN_BUBBLE_2MACRO_INSTSSIMD_UOPS_EXECSIMD_SAT_UOP_EXECSIMD_UOP_TYPE_EXECX87_OPS_RETIREDFXCH instructions retiredMACHINE_NUKESSelf-Modifying Code detectedBR_INST_RETIREDRetired branch instructionsCYCLES_INT_MASKEDCYCLES_INT_PENDING_AND_MASKEDSIMD_INST_RETIREDHW_INT_RCVHardware interrupts receivedITLB_MISS_RETIREDSIMD_COMP_INST_RETIREDMEM_LOAD_RETIREDFP_MMX_TRANSSIMD_ASSISTSIMD assists invokedSIMD_INSTR_RETIREDSIMD Instructions retiredSIMD_SAT_INSTR_RETIREDROB read port stalls cyclesSEG_RENAME_STALLSSegment rename stalls - ES SEG_REG_RENAMESSegment renames - ESRESOURCE_STALLSBR_INST_DECODEDBranch instructions decodedBOGUS_BRBogus branchesBACLEARSBACLEARS assertedPREF_RQSTS_UPPREF_RQSTS_DNROB_FULLRS_FULLLD_STFPCWBR_MISS_CLEARResource related stallsSegment renames - DSSegment renames - FSSegment renames - GSSegment rename stalls - DSSegment rename stalls - FSSegment rename stalls - GSROB_READ_PORTPARTIAL_CYCLESPartial register stall cyclesFLAGSFlag stall cyclesFPSWFPU status word stallAll RAT stall cyclesTO_FPTO_MMXL1D_LINE_MISSL2_LINE_MISSVECTORMISPRED_NOT_TAKENMISPRED_TAKENSMCMEM_ORDERLD_IND_BRSTD_STAMACRO_FUSIONNON_FUSEDNon-fused micro-ops retiredFused micro-ops retiredMicro-ops retiredFXCHANY_PSIMD pack micro-ops executedUNPACKARITHMETICSYNCHADDITIONSCISC instructions decodedSMALL_MISSLARGE_MISSITLB large page missesITLB flushesITLB missesSHAREINVALIDATESELFThis coreBOTH_CORESBoth coresAny external snoop responseExternal snoop CLEAN responseExternal snoop HIT responseExternal snoop HITM responseTHIS_AGENTThis agentALL_AGENTSAny agent on the busAny cacheline accessInvalid cachelineShared cachelineExclusive cachelineModified cachelineCORE_PBUSNO_OTHERAll inclusiveHardware prefetch onlyEXCL_PREFETCHExclude hardware prefetchL0_MISS_LDOVERLAP_STOREUNTIL_RETIREPORT_0On port 0PORT_1On port 1PORT_2On port 2PORT_3On port 3PORT_4On port 4PORT_5On port 5On any portGenuineIntelpfmlib_intel_x86.c%s (%s.%d): max_req_grpid=%d
%s (%s.%d): grpcounts[%d]=%d
ldlatintxintxcpfe_thres any=%d [0x%lx]measure any threadpfmlib_intel_x86_arch.cIntel X86 architectural PMUix86archIntel AtomUnhalted core cyclesUnhalted reference cycleLast level of cache missesBranch instructions retiredICACHEL1D_CACHEL1 Cacheable Data ReadsITLB hitsSIMD micro-ops executedMACHINE_CLEARSMacro-instructions decodedL2 cache lines evicted. External snoopsBranch address calculatorDATA_TLB_MISSESSTORE_FORWARDSAll store forwardsRetired loadsX87_COMP_OPS_EXEL2_DBUS_BUSYANY_SANY_ARGOODGood store forwardsL0_DTLB_MISS_LDDTLB_MISS_STNON_CISC_DECODEDALL_DECODEDAll Instructions decodedANY1PREFETCHT0SW_L2MUL_SMUL_ARSHIFT_SSHIFT_ARSIMD packed micro-ops retiredUNPACK_SUNPACK_ARLOGICAL_SLOGICAL_ARARITHMETIC_SARITHMETIC_ARDivide operations retiredMultiply operations retiredL1 Cacheable Data WritesSTALLED_CYCLESCycles no micro-ops retiredPeriods no micro-ops retiredpfmlib_intel_nhm_unc.cIntel Westmere uncorewsm_uncIntel Nehalem uncorenhm_uncqueue occupancyUNC_CLK_UNHALTEDUncore clockticks.UNC_DRAM_OPENUNC_GC_OCCUPANCYNumber of queue entriesUNC_DRAM_PAGE_CLOSEUNC_DRAM_PAGE_MISSDRAM Channel 0 page missUNC_DRAM_PRE_ALLUNC_DRAM_THERMAL_THROTTLEDUNC_DRAM_READ_CASUNC_DRAM_REFRESHUNC_DRAM_WRITE_CASUNC_GQ_ALLOCGQ read tracker requestsUNC_GQ_CYCLES_FULLUNC_GQ_CYCLES_NOT_EMPTYUNC_GQ_DATA_FROMCycles GQ data is importedUNC_GQ_DATA_TOCycles GQ data is exportedUNC_LLC_HITSNumber of LLC read hitsUNC_LLC_LINES_INUNC_LLC_LINES_OUTUNC_LLC_MISSNumber of LLC read missesUNC_QHL_ADDRESS_CONFLICTSQHL 2 way address conflictsUNC_QHL_CONFLICT_CYCLESUNC_QHL_CYCLES_FULLUNC_QHL_CYCLES_NOT_EMPTYUNC_QHL_FRC_ACK_CNFLTSUNC_QHL_SLEEPSUNC_QHL_OCCUPANCYUNC_QHL_REQUESTSUNC_QHL_TO_QMC_BYPASSUNC_QMC_BUSYUNC_QMC_CANCELQMC cancelsUNC_QMC_HIGH_PRIORITY_READSUNC_QMC_ISOC_FULLUNC_IMC_ISOC_OCCUPANCYUNC_QMC_NORMAL_READSQMC normal read requestsUNC_QMC_OCCUPANCYQMC OccupancyUNC_QMC_PRIORITY_UPDATESQMC priority updatesUNC_IMC_RETRYUNC_QMC_WRITESQMC cache line writesUNC_QPI_RX_NO_PPT_CREDITUNC_QPI_TX_HEADERUNC_QPI_TX_STALLED_MULTI_FLITCycles QPI outbound stallsUNC_SNP_RESP_TO_LOCAL_HOMELocal home snoop responseUNC_SNP_RESP_TO_REMOTE_HOMERemote home snoop responseUNC_THERMAL_THROTTLING_TEMPUNC_THERMAL_THROTTLED_TEMPUNC_PROCHOT_ASSERTIONUNC_TURBO_MODECORE_0CORE_1CORE_2CORE_3FWD_S_STATEFWD_I_STATEHOME_LINK_0SNOOP_LINK_0NDR_LINK_0HOME_LINK_1SNOOP_LINK_1NDR_LINK_1DRS_LINK_0NCB_LINK_0NCS_LINK_0DRS_LINK_1NCB_LINK_1NCS_LINK_1BUSY_LINK_0BUSY_LINK_1STALLS_LINK_0STALLS_LINK_1FULL_CH0FULL_CH1FULL_CH2FULL_ANYQMC full cache line writesPARTIAL_CH0PARTIAL_CH1PARTIAL_CH2PARTIAL_ANYQMC partial cache line writesAny channelREAD_CH0READ_CH1READ_CH2WRITE_CH0WRITE_CH1WRITE_CH2QMC channel 0 cancelsQMC channel 1 cancelsQMC channel 2 cancelsLOCAL_READSLOCAL_WRITESREMOTE_READSIOH_READSIOH_WRITESREMOTE_WRITESIOHIOH_ORDERREMOTE_ORDERLOCAL_ORDERIOH_CONFLICTDue to IOH address conflictsREMOTE_CONFLICTLOCAL_CONFLICTCycles QHL IOH is busy2WAY3WAYQHL 3 way address conflictsNumber of LLC write missesNumber of LLC missesF_STATELLC lines victimizedLLC lines allocatedNumber of LLC write hitsNumber of LLC peer probe hitsNumber of LLC hitsQPI_QMCCycles GQ data sent to LLCCycles GQ data sent to coresCORES_02CORES_13READ_TRACKERWRITE_TRACKERPEER_PROBE_TRACKERRT_LLC_MISSGQ read tracker LLC missesRT_TO_LLC_RESPGQ read tracker LLC requestsRT_TO_RTID_ACQUIREDWT_TO_RTID_ACQUIREDGQ write tracker LLC missesAUTOPRE_CH0AUTOPRE_CH1AUTOPRE_CH2DRAM Channel 1 page missDRAM Channel 2 page missDRAM Channel 0 page closeDRAM Channel 1 page closeDRAM Channel 2 page closeIn the read trackerUNC_QMC_NORMAL_FULLIntel Nehalem EXnhm_exIntel Nehalemnhmunknown L3 cache missreservedrequest to uncacheable memoryBR_INST_RETIRED:ALL_BRANCHESBACLEARBACLEAR_FORCE_IQBPU_CLEARSBranch prediction Unit clearsBPU_MISSED_CALL_RETBR_MISP_EXECBR_MISP_RETIREDCACHE_LOCK_CYCLESCache lock cyclesDTLB_LOAD_MISSESExtended Page DirectoryES_REG_RENAMESES segment renamesIFU_IVCINST_QUEUE_WRITESINST_QUEUE_WRITE_CYCLESIO_TRANSACTIONSI/O transactionsITLB_FLUSHITLB_MISSESInstruction TLB missesL1D cacheL1D referencesL1 data cache load lockL1D_CACHE_LOCK_FB_HITL1 data cache storesL1D hardware prefetchL1D_WB_L2L1I instruction fetchesL1I_OPPORTUNISTIC_HITSL2_DATA_RQSTSL2_HW_PREFETCHL2 HW prefetchesL2 lines allocatedL2 lines evictedL2_TRANSACTIONSL2_WRITEL2 demand lock/store RFOLARGE_ITLBLarge instruction TLBLOAD_DISPATCHLoads dispatchedLONGEST_LAT_CACHELSDLoop stream detectorMachine ClearMacro-fused instructionsMEM_INST_RETIREDMemory instructions retiredMEM_STORE_RETIREDRetired storesMEM_UNCORE_RETIREDOFFCORE_REQUESTSOffcore memory requestsOFFCORE_REQUESTS_SQ_FULLPARTIAL_ADDRESS_ALIASPIC_ACCESSESProcessor stallsSegment rename stall cyclesSIMD_INT_128SIMD_INT_64SQ_FULL_STALL_CYCLESSQ_MISCSSE_MEM_EXECStreaming SIMD executedSSEX_UOPS_RETIREDSIMD micro-ops retiredSTORE_BLOCKSDelayed loadsTWO_UOP_INSTS_DECODEDUOPS_DECODED_DEC0UOPS_DECODEDMicro-ops decodedUOPS_EXECUTEDMicro-ops executedUOPS_ISSUEDMicro-ops issuedUOP_UNFUSIONOFFCORE_RESPONSE_0PF_IFETCHANY_IFETCHPF_IFETCH:DMND_IFETCHANY_REQUESTANY_DATAANY_DATA_RDDMND_DATA_RD:PF_DATA_RDANY_RFODMND_RFO:PF_RFOUNCORE_HITOTHER_CORE_HIT_SNPOTHER_CORE_HITMREMOTE_CACHE_HITMREMOTE_CACHE_FWDANY_CACHE_DRAMANY_DRAMREMOTE_DRAM:LOCAL_DRAMANY_LLC_MISSLOCAL_CACHE_DRAMREMOTE_CACHE_DRAMUops retired (Precise Event)RETIRE_SLOTSANY:c=1ANY:c=1:i=1MACRO_FUSEDCycles stalled no issued uopsFused Uops issuedPORT0Uops executed on port 0PORT1Uops executed on port 1PORT2_COREPORT3_COREPORT4_COREUops executed on port 5PORT015PORT234_COREPORT015_STALL_CYCLESPORT015:c=1:i=1ESP_FOLDINGESP_SYNCStack pointer sync operationsMS_CYCLES_ACTIVEMS:c=1L1D_BLOCKNOT_STAVECTOR_INTEGERPROMOTIONPROMOTION_POST_GOLRU_HINTSFILL_DROPPEDThread responded HIT to snoopPACKED_ARITHPACKED_LOGICALPACKED_MPYPACKED_SHIFTSHUFFLE_MOVELoad buffer stall cyclesMXCSRMXCSR rename stall cyclesROB full stall cyclesResource related stall cyclesREGISTERSSCOREBOARDScoreboard stall cyclesTPR_READSCounts number of TPR readsTPR_WRITESCounts number of TPR writesAll offcore requestsANY_READOffcore read requestsOffcore RFO requestsDEMAND_READ_CODEDEMAND_READ_DATAOffcore demand RFO requestsL1D_WRITEBACKUNCACHED_MEMOTHER_CORE_L2_HITMREMOTE_CACHE_LOCAL_HOME_HITL3_DATA_MISS_UNKNOWNHIT_LFBL1D_HITThis is an alias for L3_MISSL3_UNSHARED_HITLLC_UNSHARED_HITOTHER_CORE_L2_HIT_HITMLATENCY_ABOVE_THRESHOLDWATCHDOGWATCH_CYCLESCycles machine clear assertedFUSION_ASSISTACTIVE:i=1Longest latency cache missAll loads dispatchedLoads dispatched from the MOBRS_DELAYEDLarge ITLB hitLOCK_E_STATELOCK_I_STATELOCK_S_STATELOCK_HITLOCK_M_STATELOCK_MESIAll demand L2 lock RFOsRFO_I_STATERFO_E_STATERFO_M_STATERFO_MESIAll L2 demand store RFOsRFO_S_STATEAll L2 transactionsL2 fill transactionsL1D_WBL2 Load transactionsL2 prefetch transactionsL2 RFO transactionsAll L2 missesAll L2 requestsIFETCH_HITL2 instruction fetch hitsIFETCH_MISSL2 instruction fetch missesIFETCHESL2 instruction fetchesLD_HITL2 load hitsL2 load missesPREFETCH_HITL2 prefetch hitsL2 prefetch missesAll L2 prefetchesL2 RFO hitsL2 RFO missesRFOSL2 RFO requestsDEMAND_CLEANDEMAND_DIRTYPREFETCH_CLEANPREFETCH_DIRTYDATA_TRIGGERCODE_TRIGGERDCA_TRIGGERKICK_STARTAll L2 data requestsDEMAND_E_STATEDEMAND_I_STATEDEMAND_M_STATEDEMAND_MESIL2 data demand requestsDEMAND_S_STATEPREFETCH_E_STATEL2 data prefetches in E statePREFETCH_I_STATEPREFETCH_M_STATEL2 data prefetches in M statePREFETCH_MESIAll L2 data prefetchesPREFETCH_S_STATECYCLES_STALLEDL1I instruction fetch hitsL1I instruction fetch missesL1I Instruction fetchesAll L1 writebacks to L2L1D hardware prefetch missesTRIGGERSL1 data cache load lock hitsL1 data cache read in E stateL1 data cache read in M stateL1 data cache readsL1 data cache read in S stateM_SNOOP_EVICTL1 data cache lines allocatedX87IQ_FULL:LCP:MRU:REGENIQ_FULLLCPMRURegen stall cyclesL1I_EVICTIONMMX UopsSSE_DOUBLE_PRECISIONSSE* FP double precision UopsSSE_FPSSE and SSE2 FP UopsSSE_FP_PACKEDSSE FP packed UopsSSE_FP_SCALARSSE FP scalar UopsSSE_SINGLE_PRECISIONSSE* FP single precision UopsSSE2_INTEGERSSE2 integer UopsEPDE_MISSEPDPE_MISSEPDPE_HITDTLB missesDTLB miss page walksPDP_MISSLARGE_WALK_COMPLETEDDTLB load missesDTLB second level hitTHREAD_PREF_PTOTAL_CYCLESTHREAD_P:c=2:i=1Cycles L1D lockedL1D_L2Cycles L1D and L2 lockedINDIRECT_NON_CALLNEAR_CALLSNON_CALLSCall branches executedTaken branches executedBAD_TARGETCYCLES_DIV_BUSY:c=1:i=1:e=1Intel Westmere DPwsm_dpwsmL3_LAT_CACHE:REFERENCEL3_LAT_CACHE:MISSBranch Prediction Unit clearsExtended Page TableLoad delayed by block codeCache lockedLast level cache accessesL3_LAT_CACHESuper Queue full stall cyclesTwo Uop instructions decodedSNOOPQ_REQUESTSSnoopq requestsOffcore requestsMISALIGN_MEMORYMisaligned accessesLSD_OVERFLOWMachine clear assertedSSE/MMX micro-opsLarge ITLB accessesITLB missSuper Queue miscellaneous128 bit SIMD operationsOFFCORE_REQUESTS_OUTSTANDINGOutstanding offcore requestsMACRO_INSTS_FUSIONS_DECODEDMacro-instructionsSB_DRAINStore bufferSNOOPQ_REQUESTS_OUTSTANDINGOutstanding snoop requestsL1I instruction fetchL1D writebacks to L2BR_MISP_RETIRED:ALL_BRANCHESCycles thread is activeOFFCORE_RESPONSE_1OTHER_LLC_MISSLOCAL_CACHEINVALIDATE_NOT_EMPTYINVALIDATE:c=1LOCAL_HITMREMOTE_HITMUNKNOWN_SOURCEAll Store buffer stall cyclesOutstanding offcore readsANY_READ_NOT_EMPTYANY_READ:c=1READ_DATA_NOT_EMPTYDEMAND_READ_DATA:c=1READ_CODE_NOT_EMPTYDEMAND_READ_CODE:c=1RFO_NOT_EMPTYDEMAND_RFO:c=1ITLB miss page walksWALK_CYCLESITLB miss page walk cyclesUOPS:c=1:i=1SSE FP double precision UopsSSE FP single precision UopsSelf-modifying code detectedSnoop code requestsSnoop data requestsSnoop invalidate requestsCYCLES_ALL_THREADSANY:c=1:t=1CORE_STALL_CYCLESANY:c=1:i=1:t=1DTLB miss large page walksDTLB miss page walk cyclesLast level cache missLast level cache referenceTotal cycles (Precise Event)ANY_P:c=16:i=1CORE_ACTIVE_CYCLES_NO_PORT5CORE_ACTIVE_CYCLESCORE_STALL_CYCLES_NO_PORT5CORE_STALL_COUNTCORE_STALL_CYCLES:e:t:i:c=1CORE_STALL_COUNT_NO_PORT5ANY:c=16:i=1Cycles no Uops are decodedIntel Sandy Bridge EPsnb_epIntel Sandy BridgesnbAGU_BYPASS_CANCELBranch re-steeredMispredicted retired branchesLocked cycles in L1D and L2CPL_CYCLESDSB2MITE_SWITCHESDSB_FILLDSB fillsDTLB_STORE_MISSESX87 Floating point assistsHW_PRE_REQHardware prefetch requestsInstruction Cache accessesIDQIDQ operationsIDQ_UOPS_NOT_DELIVEREDUops not deliveredINSTS_WRITTEN_TO_IQInstructions written to IQINT_MISCMiscellaneous internalsInstruction TLBL1D_BLOCKSL1D is blockingL1D pending missesL2_L1D_WB_RQSTSL2_STORE_LOCK_RQSTSL2 store lock requestsL2_TRANSLD_BLOCKSBlocking loadsLD_BLOCKS_PARTIALPartial load blocksMEM_LOAD_UOPS_LLC_HIT_RETIREDL3 hit loads uops retiredMEM_LOAD_LLC_HIT_RETIREDMEM_LOAD_UOPS_MISC_RETIREDMEM_LOAD_MISC_RETIREDMEM_LOAD_UOPS_RETIREDMemory loads uops retiredMEM_TRANS_RETIREDMemory transactions retiredMEM_UOPS_RETIREDMemory uops retiredMEM_UOP_RETIREDMISALIGN_MEM_REFMisaligned memory referencesOFFCORE_REQUESTS_BUFFEROffcore requests bufferOTHER_ASSISTSCount hardware assistsPARTIAL_RAT_STALLSRESOURCE_STALLS2ROB_MISC_EVENTSReorder buffer eventsRS_EVENTSReservation station eventsSIMD_FP_256SuperQ eventsUops executedUOPS_DISPATCHED_PORTUops retiredCYCLE_ACTIVITYStalled cyclesExtended page tablepage walkerCYCLES_GE_1_UOP_EXECCYCLES_GE_2_UOPS_EXECCYCLES_GE_3_UOPS_EXECCYCLES_GE_4_UOPS_EXECCORE_CYCLES_GE_1CORE:c=1CORE_CYCLES_GE_2CORE:c=2CORE_CYCLES_GE_3CORE:c=3CORE_CYCLES_GE_4CORE:c=4CORE_CYCLES_NONECORE:iUOPS:c=4CYCLES_L2_PENDINGCYCLES_L1D_PENDINGCYCLES_NO_DISPATCHCycles of dispatch stallsSTALLS_L2_PENDINGSTALLS_L1D_PENDINGPF_LLC_DATA_RDPF_LLC_IFETCHBUS_LOCKSDMND_RFO:PF_RFO:PF_LLC_RFONO_SUPPLLC_HITMLLC_HITELLC_HITFLLC_MISS_LOCAL_DRAMLLC_MISS_LOCALLLC_MISS_REMOTELLC_MISS_REMOTE_DRAMSNP_NOT_NEEDEDNO_SNP_NEEDEDSnoop: any snoop reasonALL:c=1:iALL:c=10:iPORT_2_LDPORT_2_STAPORT_0_COREPORT_0:tPORT_1_COREPORT_1:tPORT_2_COREPORT_2:tPORT_3_COREPORT_3:tPORT_4_COREPORT_4:tPORT_5_COREPORT_5:tDTLB_THREADSTLB_ANYNumber of STLB flushesSplit locks in SQEMPTY_CYCLESEMPTY_ENDEMPTY_CYCLES:c=1:e:iLBR_INSERTSALL_FL_EMPTYALL_PRF_CONTROLANY_PRF_CONTROLBOB_FULLOOO_RSRCROBFCSWMEM_RSLB:SB:RSLD_SBOOO_SRCCYCLES_FLAGS_MERGE_UOPFLAGS_MERGE_UOP:c=1MUL_SINGLE_UOPSLOW_LEA_WINDOWAVX_TO_SSESSE_TO_AVXAVX_STOREALL_DATA_RD_CYCLESALL_DATA_RD:c=1DEMAND_CODE_RD_CYCLESDEMAND_CODE_RD:c=1DEMAND_DATA_RD_CYCLESDEMAND_DATA_RD:c=1ALL_DATA_RDDEMAND_DATA_RD:c=6DEMAND_RFO_CYCLESALL_DATA_READALL_LOADSANY_LOADSALL_STORESANY_STORESLOCK_LOADSLOCK_STORESSPLIT_LOADSSPLIT_STORESSTLB_MISS_LOADSSTLB_MISS_STORESPRECISE_STOREL1_HITXSNP_HITXSNP_HITMXSNP_MISSXSNP_NONEMASKMOVMEMORY_ORDERINGSW_PFALL_STA_BLOCKDATA_UNKNOWNSTORE_FORWARDNO_SRALL_BLOCKL2_FILLL2_WBALL_PREFETCHALL_CODE_RDCODE_RD_HITCODE_RD_MISSALL_DEMAND_DATA_RDALL_DEMAND_RD_HITALL_PFRFO_ANYAny RFO requests to L2 cacheRFO_HITSDIRTY_ANYPENDING:e=1:c=1EDGEPENDING_CYCLES_ANYPENDING:c=1:tBANK_CONFLICTBANK_CONFLICT_CYCLESBANK_CONFLICT:c=1ALLOCATED_IN_MALL_M_REPLACEMENTRAT_STALL_CYCLESRECOVERY_STALLS_COUNTRECOVERY_CYCLES_ANYPREC_DISTStall cycles due to IQ fullCYCLES_0_UOPS_DELIV_CORECYCLES_GE_1_UOP_DELIV_CORECORE:c=4:iCYCLES_LE_1_UOP_DELIV_CORECYCLES_LE_2_UOP_DELIV_CORECYCLES_LE_3_UOP_DELIV_CORECYCLES_FE_WAS_OKCORE:c=1:iCycles IDQ is emptyMS_DSB_UOPSMS_MITE_UOPSMS_UOPSMS_SWITCHESMS_UOPS:c=1:eMS_DSB_UOPS_CYCLESMS_DSB_UOPS:c=1MS_MITE_UOPS_CYCLESMS_MITE_UOPS:c=1MS_UOPS_CYCLESMS_UOPS:c=1ALL_DSB_UOPSALL_DSB_CYCLESALL_DSB_CYCLES_4_UOPSALL_MITE_UOPSALL_MITE_CYCLESALL_MITE_CYCLES_4_UOPSMS_DSB_UOPS_OCCURMS_DSB_UOPS:c=1:e=1Number of X87 uops executedSSE_FP_PACKED_DOUBLESSE_FP_SCALAR_SINGLESSE_PACKED_SINGLESSE_SCALAR_DOUBLESIMD_INPUTSIMD_OUTPUTX87_INPUTX87_OUTPUTALL_CANCELEXCEED_DSB_LINESOTHER_CANCELPENALTY_CYCLESREF_XCLKREF_XCLK_ANYREF_XCLK:tONE_THREAD_ACTIVERING0RING0_TRANSRING0:c=1:e=1RING123SPLIT_LOCK_UC_LOCK_DURATIONCACHE_LOCK_DURATIONNONTAKEN_CONDTAKEN_RETURN_NEARTAKEN_DIRECT_NEAR_CALLTAKEN_INDIRECT_NEAR_CALLANY_CONDANY_DIRECT_NEAR_CALLFAR_BRANCHNEAR_TAKENTAKEN_DIRECT_JUMPAll taken non-indirect callsALL_CONDITIONALAll non-indirect callsALL_DIRECT_JMPALL_INDIRECT_NEAR_RETURNFPU_DIV_ACTIVEFPU_DIVFPU_DIV_ACTIVE:c=1:e=1snb_unc_cbo3uncore_cbox_3snb_unc_cbo2uncore_cbox_2snb_unc_cbo1uncore_cbox_1snb_unc_cbo0uncore_cbox_0UNC_CBO_XSNP_RESPONSEUNC_CBO_CACHE_LOOKUPLLC cache lookupsUNC_CLOCKTICKSuncore clock ticksSnoop responsesSTATE_MSTATE_ESTATE_SSTATE_ISTATE_MESIREAD_FILTERWRITE_FILTEREXTSNP_FILTERANY_FILTERNumber of snoop missesINVAL_MANY_SNPNumber of snoopsEXTERNAL_FILTERXCORE_FILTEREVICTION_FILTERIntel Ivy Bridge EPivb_epIntel Ivy BridgeivbMOVE_ELIMINATIONMove EliminationDTLB_LOAD_ACCESSTLB accessTLB_ACCESSMiscellaneous interruptionsOffcore reqest bufferSuperQueue miscellaneousRECOVERY_CYCLES:tCYCLES_LDM_PENDINGCYCLES_NO_EXECUTESTALLS_LDM_PENDINGALL:c=1:i=1FLAGS_MERGESLOW_LEASINGLE_MULLOAD_STLB_HITL1_MISSREMOTE_FWDAny code request to L2 cacheDEMAND_DATA_RD_HITALL_RFOPF_CLEANPF_DIRTYDIRTY_ALLINT_NOT_ELIMINATEDSIMD_NOT_ELIMINATEDINT_ELIMINATEDSIMD_ELIMINATEDIFETCH_STALLLARGE_PAGE_WALK_COMPLETEDDEMAND_LD_MISS_CAUSES_A_WALKDEMAND_LD_WALK_COMPLETEDDEMAND_LD_WALK_DURATIONTAKEN_NEAR_RETURNALL_CONDANY_DIRECT_JUMPAll direct jumpsANY_INDIRECT_NEAR_RETAll indirect near returnsivb_unc_cbo3ivb_unc_cbo2ivb_unc_cbo1ivb_unc_cbo0Intel Haswell EPhsw_epIntel HaswellhswCPU_CLK_THREAD_UNHALTEDX87 floating-point assistsHLE_RETIREDHLE execution (Precise Event)Instruction CacheL2_DEMAND_RQSTSLoad dispatchesL3 cacheMEM_LOAD_UOPS_L3_HIT_RETIREDMEM_LOAD_UOPS_L3_MISS_RETIREDSoftware assistROB miscellaneous eventsReservation StationRTM_RETIREDUOPS_EXECUTED_PORTTX_MEMTransactional memory abortsTX_EXECTransactional executionPAGE_WALKER_LOADSPage walker loadsCounts AVX instructionsDIVIDER_UOPSEPT_DTLB_L1EPT_ITLB_L1EPT_DTLB_L2EPT_ITLB_L2EPT_DTLB_L3EPT_ITLB_L3EPT_DTLB_MEMORYEPT_ITLB_MEMORYABORT_CONFLICTABORT_CAPACITY_WRITEABORT_HLE_ELISION_BUFFER_FULLABORTED_MISC1ABORTED_MISC2ABORTED_MISC3ABORTED_MISC4ABORTED_MISC5DMND_CODE_RDPF_CODE_RDPF_L3_DATA_RDPF_L3_CODE_RDPF_L3_IFETCHSPLIT_LOCK_UC_LOCKANY_CODE_RDDMND_RFO:PF_RFO:PF_L3_RFOL3_HITML3_HITEL3_HITFL3_HITM:L3_HITE:L3_HITSL3_MISS_REMOTE_HOP0L3_MISS_REMOTE_HOP1L3_MISS_REMOTE_HOP2PL3_MISS_REMOTEL3_MISS_REMOTE_DRAMSPL_HITALL:i=1:c=1ALL:i=1:c=10ALL:i=1:c=1:t=1STALL_OCCURRENCESALL:c=1:i=1:e=1PORT_6PORT_7tbdPORT_0:t=1PORT_1:t=1PORT_2:t=1PORT_3:t=1PORT_4:t=1PORT_5:t=1PORT_6_COREPORT_6:t=1PORT_7_COREPORT_7:t=1ANY_WB_ASSISTAll load uops retiredAll store uops retiredLOAD_LATENCYCYCLES:c=1:ecycles that the L1D is lockedALL_REQUESTSDEMAND_DATA_RD_MISSDEMAND_RFO_MISSDEMAND_RFO_HITALL_DEMAND_MISSL2_PF_MISSL2_PF_HITALL_DEMAND_REFERENCESAll requests to L2 cacheL2 cache lines filling L2WB_HITWB requests that hit L2 cacheNumber L1D miss outstandingPENDING:c=1:e=1REQUEST_FB_FULLREQUEST_FB_FULL:c=1L1D Data line replacementsMS_DSB_OCCURALL_DSB_CYCLES_ANY_UOPSALL_MITE_CYCLES_ANY_UOPSWALK_COMPLETED_4KWALK_COMPLETED_2M_4MSTLB_HIT_4KSTLB_HIT_2MPDE_CACHE_MISSNONTAKEN_CONDITIONALTAKEN_INDIRECT_NEAR_RETURNALL_DIRECT_NEAR_CALLIntel Broadwell EPbdw_epIntel BroadwellbdwArithmetic uopFP_ARITHFP_ARITH_INST_RETIREDUOPS_DISPATCHES_CANCELLEDMicro-ops cancelledSIMD_PRFSCALAR_DOUBLE:SCALAR_SINGLE128B_PACKED_DOUBLE128B_PACKED_SINGLE256B_PACKED_DOUBLE256B_PACKED_SINGLEABORT_CAPACITYAlias for L3_HITMESFAlias for LLC_HITMESFL3_MISS_REMOTE_HOP0_DRAML3_MISS_REMOTE_HOP1_DRAML3_MISS_REMOTE_HOP2P_DRAMTHREAD:c=1:iTHREAD:c=1THREAD:c=2THREAD:c=3THREAD:c=4PREC_DIST:i=1:c=10IFDATA_STALLWALK_COMPLETED_1GCYCLES_MEM_ANYSTALLS_TOTALIntel CascadeLake XclxIntel Skylake XskxIntel SkylakesklICACHE_16BICACHE_64BMEM_LOAD_L3_HIT_RETIREDMEM_LOAD_L3_MISS_RETIREDEXE_ACTIVITYExecution activityFRONTEND_RETIREDPrecise Front-End activityHW_INTERRUPTSLoad retired miscellaneousIDI_MISCCORE_POWERPower power cyclesSW_PREFETCHSW_PREFETCH_ACCESSCORE_SNOOP_RESPONSEAggregated core snoopsRAT stallsINDIRECTRSP_IHITIRSP_IHITFSERSP_SHITFSERSP_SFWDMRSP_IFWDMRSP_IFWDFERSP_SFWDFEPREFETCHWLVL0_TURBO_LICENSELVL1_TURBO_LICENSELVL2_TURBO_LICENSEWB_UPGRADEWB_DOWNGRADEANY_DSB_MISSL1I_MISSSTLB_MISSIDQ_4_BUBBLESIDQ_3_BUBBLESIDQ_2_BUBBLESIDQ_1_BUBBLE1_PORTS_UTIL2_PORTS_UTIL4_PORTS_UTILBOUND_ON_STORESEXE_BOUND_0_PORTS512B_PACKED_DOUBLE512B_PACKED_SINGLEWALK_PENDINGCYCLES_WITH_DEMAND_CODE_RDCYCLES_WITH_DEMAND_DATA_RDCYCLES_WITH_DEMAND_RFOL3_MISS_DEMAND_DATA_RDL3_MISS_DEMAND_DATA_RD_GE_6ABORTED_MEMABORTED_TMRABORTED_UNFRIENDLYABORTED_MEMTYPEABORTED_EVENTSPF_L2_DATA_RDPF_L2_RFOPF_L1D_AND_SWANY_DATA_PFDMND_RFO:PF_L2_RFO:PF_L3_RFOSUPPLIER_NONEAlias for L3_HITMESL4_HIT_LOCAL_L4Supplier: L4 local hitSupplier: counts L3 missesSnoop: counts L3 supplier hitSNP_HIT_NO_FWDSNP_HIT_WITH_FWDALL:c=1:i:t=1VECTOR_WIDTH_MISMATCHTHREAD_CYCLES_GE_1THREAD_CYCLES_GE_2THREAD_CYCLES_GE_3THREAD_CYCLES_GE_4PAUSE_INSTNON_SILENTUSELESS_HWPREFUSELESS_HWPFRECOVERY_CYCLES:e:c=1CLEAR_RESTEER_CYCLESCYCLES_LE_1_UOPS_DELIV_CORECYCLES_LE_2_UOPS_DELIV_CORECYCLES_LE_3_UOPS_DELIV_COREIFTAG_HITIFTAG_MISSIFTAG_STALLWALK_ACTIVEWALK_PENDING:c=1CYCLES_L2_MISSCYCLES_L3_MISSCYCLES_L1D_MISSSTALLS_L1D_MISSSTALLS_L2_MISSSTALLS_L3_MISSSTALLS_MEM_ANYTHREAD_P:e:c=1Intel IcelakeXicxIntel IcelakeiclSuperQueue miscellaneous.L2 lines evicted.L2 lines allocated.L2 transactions.Branch re-steers.L3 hit load uops retired.Retired load uops.Memory instructions retired.Memory transactions retired,Miscellaneous retired events.Branch instructions retired.Machine clear asserted.Retired uops.Software assist.Data TLB flushes.Uops executed.Requests sent to uncore.Execution activity,Stalled cycles.Uops not delivered.Instruction TLB misses.Instruction Cache.Outstanding offcore requests.Reservation Station.Transactional execution.Transactional memory.L1D cache.LOAD_HIT_PREFETCHLoad dispatches.Data TLB store misses.L1D pending misses.Software prefetches.L3 cache.Power power cycles.L2 requests.Arithmetic uops.Uops issued.Miscellaneous interruptions.Data TLB load misses.Partial load blocks.Blocking loads.TOPDOWNTOPDOWN_MMiscellaneous loads retiredInstructions decodersOffcore response eventOCRDECODERSCYCLES_WITH_DATA_RDNOPREF_DISTRIBUTEDREF_TSCBACKEND_BOUNDBAD_SPECFRONTEND_BOUNDBR_MISPREDICT_SLOTSBACKEND_BOUND_SLOTSSLOTS_PUOP_DROPPINGALL_RECOVERY_CYCLESCLEARS_COUNTClears speculative countUops that RAT issues to RSDemand requests to L2 cacheL2 code requestsDemand Data Read requestsSWPF_HITSWPF_MISSL2_STALLFB_FULL_PERIODSABORT_CAPACITY_READMS_CYCLES_ANYDSB_CYCLES_ANYDSB_CYCLES_OKMITE_CYCLES_ANYMITE_CYCLES_OKPORT_7_8PORT_4_9PORT_2_3Total execution stalls.STLB flush attemptsRetirement slots used.COND_NTAKENReturn instructions retired.COND_TAKENINDIRECT_CALLLATENCY_GE_1LATENCY_GE_2_BUBBLES_GE_1LATENCY_GE_512LATENCY_GE_256LATENCY_GE_128LATENCY_GE_64LATENCY_GE_32LATENCY_GE_16LATENCY_GE_8LATENCY_GE_4LATENCY_GE_24_FLOPS8_FLOPSBUS_LOCKWRITE_ESTIMATE_MEMORYREADS_TO_CORE_REMOTE_MEMORYHWPF_L2_ANY_RESPONSEREADS_TO_CORE_SNC_CACHE_HITMDEMAND_CODE_RD_SNC_CACHE_HITMDEMAND_RFO_SNC_CACHE_HITMDEMAND_DATA_RD_SNC_CACHE_HITMPREFETCHES_L3_HITPREFETCHES_L3_MISS_LOCALHWPF_L3_L3_MISSSTREAMING_WR_L3_MISSREADS_TO_CORE_L3_MISSDEMAND_RFO_L3_MISSHWPF_L3_REMOTEREADS_TO_CORE_REMOTEITOM_L3_MISS_LOCALHWPF_L3_L3_MISS_LOCALSTREAMING_WR_L3_MISS_LOCALREADS_TO_CORE_L3_MISS_LOCALDEMAND_RFO_L3_MISS_LOCALREADS_TO_CORE_L3_HITHWPF_L3_L3_HITSTREAMING_WR_L3_HITREADS_TO_CORE_ANY_RESPONSEDEMAND_RFO_ANY_RESPONSEREADS_TO_CORE_SNC_DRAMDEMAND_CODE_RD_SNC_DRAMDEMAND_RFO_SNC_DRAMDEMAND_DATA_RD_SNC_DRAMREADS_TO_CORE_SNC_PMMREADS_TO_CORE_LOCAL_PMMREADS_TO_CORE_REMOTE_PMMREADS_TO_CORE_REMOTE_DRAMREADS_TO_CORE_LOCAL_DRAMREADS_TO_CORE_DRAMHWPF_L1D_AND_SWPF_L3_HITDEMAND_CODE_RD_L3_HITDEMAND_RFO_L3_HITDEMAND_DATA_RD_L3_HITDEMAND_RFO_SNC_PMMDEMAND_DATA_RD_SNC_PMMOTHER_L3_MISS_LOCALHWPF_L1D_AND_SWPF_DRAMDEMAND_CODE_RD_L3_MISS_LOCALDEMAND_CODE_RD_DRAMDEMAND_RFO_PMMDEMAND_RFO_LOCAL_PMMDEMAND_RFO_REMOTE_PMMDEMAND_RFO_DRAMDEMAND_DATA_RD_PMMDEMAND_DATA_RD_LOCAL_PMMDEMAND_DATA_RD_L3_MISS_LOCALDEMAND_DATA_RD_REMOTE_PMMDEMAND_DATA_RD_DRAMDEMAND_DATA_RD_REMOTE_DRAMHWPF_L3_ANY_RESPONSEOTHER_L3_MISSOTHER_ANY_RESPONSESTREAMING_WR_ANY_RESPONSEHWPF_L1D_AND_SWPF_LOCAL_DRAMHWPF_L1D_AND_SWPF_L3_MISSDEMAND_CODE_RD_LOCAL_DRAMDEMAND_CODE_RD_L3_MISSDEMAND_CODE_RD_ANY_RESPONSEDEMAND_RFO_LOCAL_DRAMDEMAND_DATA_RD_LOCAL_DRAMDEMAND_DATA_RD_L3_MISSDEMAND_DATA_RD_ANY_RESPONSEDEMAND_RFO_L3_HIT_SNOOP_HITMOTHER_LOCAL_DRAMSTREAMING_WR_LOCAL_DRAMHWPF_L2_RFO_LOCAL_DRAMHWPF_L2_DATA_RD_LOCAL_DRAMHWPF_L2_RFO_L3_MISSHWPF_L2_DATA_RD_L3_MISSOTHER_DRAMSTREAMING_WR_DRAMHWPF_L2_RFO_DRAMHWPF_L2_DATA_RD_DRAMOTHER_L3_HIT_SNOOP_SENTHWPF_L2_RFO_L3_HIT_SNOOP_SENTDEMAND_RFO_L3_HIT_SNOOP_SENTHWPF_L2_RFO_ANY_RESPONSEHWPF_L2_DATA_RD_ANY_RESPONSEHWPF_L3_L3_HIT_ANYOTHER_L3_HIT_SNOOP_HIT_NO_FWDOTHER_L3_HIT_SNOOP_MISSOTHER_L3_HIT_SNOOP_NOT_NEEDEDSTREAMING_WR_L3_HIT_ANYHWPF_L1D_AND_SWPF_L3_HIT_ANYHWPF_L2_RFO_L3_HIT_ANYHWPF_L2_RFO_L3_HIT_SNOOP_HITMHWPF_L2_RFO_L3_HIT_SNOOP_MISSHWPF_L2_DATA_RD_L3_HIT_ANYDEMAND_CODE_RD_L3_HIT_ANYDEMAND_RFO_L3_HIT_ANYDEMAND_RFO_L3_HIT_SNOOP_MISSDEMAND_DATA_RD_L3_HIT_ANYIntel EmeraldRapidemrIntel SapphireRapidsprINT_VEC_RETIREDMISC2_RETIREDFP_ARITH_INST_RETIRED2Excution cycles.FP_ARITH_DISPATCHEDUops dispatched.Arithmetic operations.Execution activity.RS_EMPTYIDQ_BUBBLESDecoder activity.ICACHE_TAGInstruction cache tagging.ICACHE_DATAInstruction cache.Uops decoded.Instruction decoded.DSB to MITE switches.MEMORY_ACTIVITYMemory activity.MEM_LOAD_COMPLETEDCompleted demand load.Offcore requests.Topdown events.Cycles in unhalted state.REP_ITERATIONC01C02C0_WAITPAUSEREF_TSC_PBR_MISPREDICTFETCH_LATHEAVY_OPSMEMORY_BOUNDBAD_SPEC_SLOTSMEMORY_BOUND_SLOTSL1_MISS_ANYL2_STALLSDEC0_UOPSSTALL_PERIODSMS_BUSYEMPTY_COUNTBOUND_ON_LOADSMBA_STALLSUNKNOWN_BRANCH_CYCLESFPDIV_ACTIVEFP_DIVIDER_ACTIVEIDIV_ACTIVEINT_DIVIDER_ACTIVEPORT_2_3_10PORT_5_11Uops executed on port 6AMX_BUSYPAGE_FAULTSSE_AVX_MIXCycles with retired uop(s).HEAVYMS_FLOWSUNKNOWN_BRANCHSTORE_SAMPLE128B_PACKED_HALF256B_PACKED_HALF512B_PACKED_HALFCOMPLEX_SCALAR_HALFXSNP_FWDXSNP_NO_FWDLFENCELFENCE instructions retired128BIT256BITADD_128ADD_256MUL_256SHUFFLESVNNI_128VNNI_256HWPF_L1D_ANY_RESPONSEMODIFIED_WRITE_ANY_RESPONSERFO_TO_CORE_L3_HIT_MIntel GraniteRapidsgnrCounts all hardware assists.Retired memory instructions.Retired load operations.Retired store operationsMemory transactions retired.Retired memory uops.Offcore response event.Miscellaneous SQ activity.Software prefetch accesses.Topdown event.Uops disaptched.Uops ecxecuted.Uops retired.Xq activity.EMPTY_RESOURCELOAD_LATENCY_GT_1024LOAD_LATENCY:ldlat=1024LOAD_LATENCY_GT_128LOAD_LATENCY:ldlat=128LOAD_LATENCY_GT_16LOAD_LATENCY:ldlat=16LOAD_LATENCY_GT_2048LOAD_LATENCY:ldlat=2048LOAD_LATENCY_GT_256LOAD_LATENCY:ldlat=256LOAD_LATENCY_GT_32LOAD_LATENCY:ldlat=32LOAD_LATENCY_GT_4LOAD_LATENCY:ldlat=4LOAD_LATENCY_GT_512LOAD_LATENCY:ldlat=512LOAD_LATENCY_GT_64LOAD_LATENCY:ldlat=64LOAD_LATENCY_GT_8LOAD_LATENCY:ldlat=8Retired load instructions.Retired store instructions.STLB_HIT_LOADSSTLB_HIT_STORESALL_HWPFHWPF_MISSRetired NOP instructions.ANY_ANTRetired ANT branchesLATE_SWPFMISP_ANTV0V1V22_3_PORTS_UTILALL_BRANCHES_COSTCOND_COSTCOND_NTAKEN_COSTCOND_TAKEN_COSTINDIRECT_CALL_COSTINDIRECT_COSTNEAR_TAKEN_COSTRET_COSTHARDWARE[0x%lx event=0x%x] %s
Intel RAPLpowerRAPL_ENERGY_PKGRAPL_ENERGY_DRAMRAPL_ENERGY_CORESRAPL_ENERGY_GPURAPL_ENERGY_PSYSpfmlib_intel_snbep_unc.ctfcfffisocnfaddr:%s=0x%lxremlocrmemlmemdnidrcsnidocc_iocc_eedge detectthreshold in range [0-255]threshold in range [0-31]thread id filter [0-1]frequency >= 100Mhz * [0-255]match isochronous requestsmatch non-coherent requeststhread id filter [0-3]source id filter [0-63]match on local node targetmatch on remote node targetlocal memory cacheableremote memory cacheabledestination node id [0-15]threshold in range [0-63]occupancy event invertoccupancy event edge snbep_unc_cbo7uncore_cbox_7snbep_unc_cbo6uncore_cbox_6snbep_unc_cbo5uncore_cbox_5snbep_unc_cbo4uncore_cbox_4snbep_unc_cbo3snbep_unc_cbo2snbep_unc_cbo1snbep_unc_cbo0UNC_C_CLOCKTICKSC-box Uncore clockticksUNC_C_COUNTER0_OCCUPANCYUNC_C_ISMQ_DRD_MISS_OCCUNC_C_LLC_LOOKUPUNC_C_LLC_VICTIMSLines victimizedUNC_C_MISCMiscellaneous C-Box eventsUNC_C_RING_AD_USEDUNC_C_RING_AK_USEDUNC_C_RING_BL_USEDUNC_C_RING_BOUNCESUNC_C_RING_IV_USEDUNC_C_RING_SRC_THRTLTDBUNC_C_RXR_EXT_STARVEDUNC_C_RXR_INSERTSUNC_C_RXR_IPQ_RETRYProbe Queue RetriesUNC_C_RXR_IRQ_RETRYIngress Request Queue RejectsUNC_C_RXR_ISMQ_RETRYISMQ RetriesUNC_C_RXR_OCCUPANCYUNC_C_TOR_INSERTSTOR InsertsUNC_C_TOR_OCCUPANCYTOR OccupancyUNC_C_TXR_ADS_USEDEgress eventsUNC_C_TXR_INSERTSEgress allocationsAD_CACHEAK_CACHEBL_CACHEIV_CACHEAD_COREAK_COREBL_COREAll valid TOR entriesNID_ALLNID_EVICTIONNID_MISS_ALLNID_MISS_OPCODENID_OPCODEOPC_RFOOPC_CRDOPC_DRDOPC_PRDOPC_WCILFOPC_WCILOPC_PF_RFOOPC_PF_CODEOPC_PF_DATAOPC_PCIWILFOPC_PCIPRDOPC_PCIITOMOPC_PCIRDCUROPC_ITOMOPC_PCINSRDOPC_PCINSWROPC_PCINSWRFNID_WBAny rejectNo Egress creditsIIO_CREDITSNo IIO creditsQPI_CREDITSNO QPI creditsRTIDADDR_CONFLICTAddress conflictNo QPI creditsIRQ_REJECTEDIRQ rejectedVFIFOISMQISMQ_BIDSNumber of time the ISMQ bidsAny filterAcknowledgment to coreData response to coreSnoops of processor cacheDOWN_EVENDOWN_ODDRSPI_WAS_FSESilent snoop evictionWC_ALIASINGWrite combining aliasingSTARTEDRFO_HIT_SRFO hits in S stateLines in M stateLines in E stateLines in S stateNIDAny requestData read requestsREMOTE_SNOOPExternal snoop requestSTATE_FSTATE_MESIFAny cache line state[UNC_HA_OPC=0x%lx opc=0x%x]
snbep_unc_hauncore_haUNC_H_CLOCKTICKSHA Uncore clockticksUNC_H_CONFLICT_CYCLESConflict ChecksUNC_H_DIRECT2CORE_COUNTDirect2Core Messages SentUNC_H_DIRECTORY_LOOKUPDirectory LookupsUNC_H_DIRECTORY_UPDATEDirectory UpdatesUNC_H_IGR_NO_CREDIT_CYCLESUNC_H_IMC_RETRYRetry EventsUNC_H_IMC_WRITESUNC_H_REQUESTSRead and Write RequestsUNC_H_TAD_REQUESTS_G0UNC_H_TAD_REQUESTS_G1UNC_H_TRACKER_INSERTSTracker AllocationsUNC_H_TXR_ADUNC_H_TXR_AD_CYCLES_FULLAD Egress FullUNC_H_TXR_AK_CYCLES_FULLAK Egress FullUNC_H_TXR_AK_NDRUNC_H_TXR_BLUNC_H_TXR_BL_CYCLES_FULLBL Egress FullDRS_CACHEDRS_COREDRS_QPISCHED0SCHED1Counts non-data responsesCounts all requestsREGION8Counts for TAD Region 8REGION9Counts for TAD Region 9REGION10Counts for TAD Region 10REGION11Counts for TAD Region 11REGION0Counts for TAD Region 0REGION1Counts for TAD Region 1REGION2Counts for TAD Region 2REGION3Counts for TAD Region 3REGION4Counts for TAD Region 4REGION5Counts for TAD Region 5REGION6Counts for TAD Region 6REGION7Counts for TAD Region 7CHN0CHN1CHN2channel 2CHN3Chanell 3Counts incoming writesCounts all writesCounts full line non ISOCHCounts ISOCH full lineCounts partial non-ISOCHCounts ISOCH partialAD_QPI0AD to QPI link 0AD_QPI1AD to QPI link 1BL_QPI0BL to QPI link 0BL_QPI1BL to QPI link 1Counts any directory updateDirectory clearsDirectory setNO_SNPSnoop not neededSnoop neededNO_CONFLICTsnbep_unc_imc3uncore_imc_3snbep_unc_imc2uncore_imc_2snbep_unc_imc1uncore_imc_1snbep_unc_imc0uncore_imc_0UNC_M_CLOCKTICKSIMC Uncore clockticksUNC_M_ACT_COUNTDRAM Activate CountUNC_M_CAS_COUNTUNC_M_DRAM_PRE_ALLDRAM Precharge All CommandsUNC_M_DRAM_REFRESHUNC_M_ECC_CORRECTABLE_ERRORSECC Correctable ErrorsUNC_M_MAJOR_MODESCycles in a Major ModeUNC_M_POWER_CHANNEL_DLLOFFChannel DLLOFF CyclesUNC_M_POWER_CHANNEL_PPDChannel PPD CyclesUNC_M_POWER_CKE_CYCLESCKE_ON_CYCLES by RankCritical Throttle CyclesUNC_M_POWER_SELF_REFRESHClock-Enabled Self-RefreshUNC_M_POWER_THROTTLE_CYCLESThrottle Cycles for Rank 0UNC_M_PREEMPTIONRead Preemption CountUNC_M_PRE_COUNTDRAM Precharge commands.UNC_M_RPQ_CYCLES_FULLUNC_M_RPQ_CYCLES_NERead Pending Queue Not EmptyUNC_M_RPQ_INSERTSUNC_M_RPQ_OCCUPANCYRead Pending Queue OccupancyUNC_M_WPQ_CYCLES_FULLUNC_M_WPQ_CYCLES_NEWrite Pending Queue Not EmptyUNC_M_WPQ_INSERTSUNC_M_WPQ_OCCUPANCYWrite Pending Queue OccupancyUNC_M_WPQ_READ_HITWrite Pending Queue CAM MatchUNC_M_WPQ_WRITE_HITRD_PREEMPT_RDRD_PREEMPT_WRCount cycles for rank 0Count cycles for rank 1Count cycles for rank 2Count cycles for rank 3Count cycles for rank 4Count cycles for rank 5Count cycles for rank 6Count cycles for rank 7PANICRD_REGRD_UNDERFILLWR_RMMWR_WMMsnbep_unc_pcuuncore_pcuUNC_P_CLOCKTICKSPCU Uncore clockticksUNC_P_CORE0_TRANSITION_CYCLESUNC_P_CORE1_TRANSITION_CYCLESUNC_P_CORE2_TRANSITION_CYCLESUNC_P_CORE3_TRANSITION_CYCLESUNC_P_CORE4_TRANSITION_CYCLESUNC_P_CORE5_TRANSITION_CYCLESUNC_P_CORE6_TRANSITION_CYCLESUNC_P_CORE7_TRANSITION_CYCLESUNC_P_DEMOTIONS_CORE0Core C State DemotionsUNC_P_DEMOTIONS_CORE1UNC_P_DEMOTIONS_CORE2UNC_P_DEMOTIONS_CORE3UNC_P_DEMOTIONS_CORE4UNC_P_DEMOTIONS_CORE5UNC_P_DEMOTIONS_CORE6UNC_P_DEMOTIONS_CORE7UNC_P_FREQ_BAND0_CYCLESFrequency ResidencyUNC_P_FREQ_BAND1_CYCLESUNC_P_FREQ_BAND2_CYCLESUNC_P_FREQ_BAND3_CYCLESUNC_P_FREQ_MAX_CURRENT_CYCLESUNC_P_FREQ_MAX_OS_CYCLESUNC_P_FREQ_MAX_POWER_CYCLESUNC_P_FREQ_MIN_IO_P_CYCLESUNC_P_FREQ_MIN_PERF_P_CYCLESUNC_P_FREQ_TRANS_CYCLESMemory Phase Shedding CyclesUNC_P_POWER_STATE_OCCUPANCYNumber of cores in C0UNC_P_PROCHOT_EXTERNAL_CYCLESExternal ProchotUNC_P_PROCHOT_INTERNAL_CYCLESInternal ProchotUNC_P_TOTAL_TRANSITION_CYCLESCycles Changing VoltageCycles Decreasing VoltageCycles Increasing VoltageUNC_P_VR_HOT_CYCLESVR HotCounts number of cores in C0Counts number of cores in C3Counts number of cores in C6CORES_C0CORES_C3CORES_C6snbep_unc_qpi1uncore_qpi_1snbep_unc_qpi0uncore_qpi_0UNC_Q_CLOCKTICKSNumber of qfclksUNC_Q_CTO_COUNTCount of CTO EventsUNC_Q_DIRECT2COREDirect 2 Core SpawningUNC_Q_L1_POWER_CYCLESCycles in L1UNC_Q_RXL0P_POWER_CYCLESCycles in L0pUNC_Q_RXL0_POWER_CYCLESCycles in L0UNC_Q_RXL_BYPASSEDRx Flit Buffer BypassedVN0 Credit ConsumedVNA Credit ConsumedUNC_Q_RXL_CYCLES_NERxQ Cycles Not EmptyUNC_Q_RXL_FLITS_G0Flits Received - Group 0UNC_Q_RXL_FLITS_G1Flits Received - Group 1UNC_Q_RXL_FLITS_G2Flits Received - Group 2UNC_Q_RXL_INSERTSRx Flit Buffer AllocationsUNC_Q_RXL_INSERTS_DRSUNC_Q_RXL_INSERTS_HOMUNC_Q_RXL_INSERTS_NCBUNC_Q_RXL_INSERTS_NCSUNC_Q_RXL_INSERTS_NDRUNC_Q_RXL_INSERTS_SNPUNC_Q_RXL_OCCUPANCYRxQ Occupancy - All PacketsUNC_Q_RXL_OCCUPANCY_DRSRxQ Occupancy - DRSUNC_Q_RXL_OCCUPANCY_HOMRxQ Occupancy - HOMUNC_Q_RXL_OCCUPANCY_NCBRxQ Occupancy - NCBUNC_Q_RXL_OCCUPANCY_NCSRxQ Occupancy - NCSUNC_Q_RXL_OCCUPANCY_NDRRxQ Occupancy - NDRUNC_Q_RXL_OCCUPANCY_SNPRxQ Occupancy - SNPUNC_Q_TXL0P_POWER_CYCLESUNC_Q_TXL0_POWER_CYCLESUNC_Q_TXL_BYPASSEDTx Flit Buffer BypassedUNC_Q_TXL_CYCLES_NEUNC_Q_TXL_FLITS_G0Flits Transferred - Group 0UNC_Q_TXL_FLITS_G1Flits Transferred - Group 1UNC_Q_TXL_FLITS_G2Flits Transferred - Group 2UNC_Q_TXL_INSERTSTx Flit Buffer AllocationsUNC_Q_TXL_OCCUPANCYTx Flit Buffer OccupancyUNC_Q_VNA_CREDIT_RETURNSVNA Credits ReturnedNCB_DATANCB_NONDATANDR_ADNDR_AKDRS_DATADRS_NONDATAHOM_NONREQHOM_REQNumber of data flits over QPIFAILURE_CREDITSFAILURE_CREDITS_RBTFAILURE_RBTNumber of spawn successessnbep_unc_ubouncore_uboxUNC_U_EVENT_MSGVLW ReceivedUNC_U_LOCK_CYCLESIDI Lock/SplitLock CyclesDOORBELL_RCVDINT_PRIOIPI_RCVDMSI_RCVDVLW_RCVDsnbep_unc_r2pcieuncore_r2pcieUNC_R2_CLOCKTICKSNumber of uclks in domainUNC_R2_RING_AD_USEDR2 AD Ring in UseUNC_R2_RING_AK_USEDR2 AK Ring in UseUNC_R2_RING_BL_USEDR2 BL Ring in UseUNC_R2_RING_IV_USEDR2 IV Ring in UseUNC_R2_RXR_AK_BOUNCESAK Ingress BouncedUNC_R2_RXR_CYCLES_NEUNC_R2_TXR_CYCLES_FULLEgress Cycles FullUNC_R2_TXR_CYCLES_NEEgress Cycles Not EmptyUNC_R2_TXR_INSERTSAD Egress queueAK Egress queueBL Egress queueDRS Ingress queueNCB Ingress queueNCS Ingress queueCCW_EVENCCW_ODDClockwise with any polarityCCW_ANYsnbep_unc_r3qpi1uncore_r3qpi_1snbep_unc_r3qpi0uncore_r3qpi_0UNC_R3_CLOCKTICKSUNC_R3_IIO_CREDITS_ACQUIREDto IIO BL Credit AcquiredUNC_R3_IIO_CREDITS_REJECTto IIO BL Credit RejectedUNC_R3_IIO_CREDITS_USEDto IIO BL Credit In UseUNC_R3_RING_AD_USEDR3 AD Ring in UseUNC_R3_RING_AK_USEDR3 AK Ring in UseUNC_R3_RING_BL_USEDR3 BL Ring in UseUNC_R3_RING_IV_USEDR3 IV Ring in UseUNC_R3_RXR_BYPASSEDIngress BypassedUNC_R3_RXR_CYCLES_NEUNC_R3_RXR_INSERTSUNC_R3_RXR_OCCUPANCYIngress Occupancy AccumulatorUNC_R3_TXR_CYCLES_FULLEgress cycles fullUNC_R3_TXR_INSERTSUNC_R3_TXR_NACKEgress NackUNC_R3_VN0_CREDITS_REJECTUNC_R3_VN0_CREDITS_USEDVN0 Credit UsedUNC_R3_VNA_CREDITS_ACQUIREDVNA credit AcquisitionsUNC_R3_VNA_CREDITS_REJECTVNA Credit RejectUNC_R3_VNA_CREDIT_CYCLES_OUTUNC_R3_VNA_CREDIT_CYCLES_USEDFilter DRS message classFilter HOM message classFilter NCB message classFilter NCS message classFilter NDR message classFilter SNP message classHOM Ingress queueNDR Ingress queueSNP Ingress queueAny polarityivbep_unc_cbo14uncore_cbox_14ivbep_unc_cbo13uncore_cbox_13ivbep_unc_cbo12uncore_cbox_12ivbep_unc_cbo11uncore_cbox_11ivbep_unc_cbo10uncore_cbox_10ivbep_unc_cbo9uncore_cbox_9ivbep_unc_cbo8uncore_cbox_8ivbep_unc_cbo7ivbep_unc_cbo6ivbep_unc_cbo5ivbep_unc_cbo4ivbep_unc_cbo3ivbep_unc_cbo2ivbep_unc_cbo1ivbep_unc_cbo0Cache lookupsonto AD ringOnto AK ringOnto BL ringMISS_LOCAL_OPCODEMISS_REMOTE_OPCODEWB_CREDITSNo WB creditsNo IIO CreditsFilter on any up polarityFilter on any down polarityAD_IRQAcknowledgments to coreData responses to coreUP_VR0_EVENUP_VR0_ODDDOWN_VR0_EVENDOWN_VR0_ODDUP_VR1_EVENUP_VR1_ODDDOWN_VR1_EVENDOWN_VR1_ODDUp on any virtual ringDown any virtual ringivbep_unc_ha1uncore_ha_1ivbep_unc_ha0uncore_ha_0UNC_H_IMC_READSIMC RPQ Credits EmptyHA Requests to a TAD RegionUNC_H_TXR_AKHA IMC CHN0 WPQ Credits EmptyUNC_H_BT_BYPASSBackup Tracker bypassUNC_H_BYPASS_IMCHA to IMC bypassUNC_H_BT_CYCLES_NEUNC_H_BT_OCCUPANCYBackup Tracker insertsUNC_H_IGR_AD_QPI2UNC_H_IGR_BL_QPI2UNC_H_IODC_INSERTSIODC insertsUNC_H_IODC_CONFLICTSIODC conflictsUNC_H_IODC_OLEN_WBMTOIIODC zero length writesUNC_H_OSBOSB snoop broadcastUNC_H_OSB_EDROSB early data returnUNC_H_RING_AD_USEDAD ring in useUNC_H_RING_AK_USEDAK ring in useUNC_H_RING_BL_USEDBL ring in useUNC_H_DIRECTORY_LAT_OPTUNC_H_SNP_RESP_RECV_LOCALUNC_H_TXR_BL_OCCUPANCYBL Egress occupancyUNC_H_SNOOP_RESPSnoop responses receivedAny conflictLASTLast conflictCRD_CBOCRD_QPIRSPIRSPSRSPIFWDRSPSFWDRSP_WBRSP_FWD_WBRSPCNFLCTCCW_VR0_EVENCCW_VR0_ODDCCW_VR1_EVENCCW_VR1_ODDAll data returnsREADS_LOCAL_IReads to local IREADS_REMOTE_IReads to remote IREADS_LOCAL_SReads to local SREADS_REMOTE_SReads to remote SREADS_LOCALLocal readsINVITOE_LOCALLocal InvItoELocalREADS_REMOTEReads remoteWRITES_LOCALWrites localWRITES_REMOTEWrites remoteINVITOE_REMOTENormal priorityBypass takenBypass not takenSNooop neededCMP_FWDSACKCNFLTSCount the number Acknfltsivbep_unc_imc7uncore_imc_7ivbep_unc_imc6uncore_imc_6ivbep_unc_imc5uncore_imc_5ivbep_unc_imc4uncore_imc_4ivbep_unc_imc3ivbep_unc_imc2ivbep_unc_imc1ivbep_unc_imc0UNC_M_DCLOCKTICKSUNC_M_BYP_CMDSBypass command eventUNC_M_RD_CAS_PRIORead CAS priorityUNC_M_RD_CAS_RANK0Read CAS access to Rank 0UNC_M_RD_CAS_RANK1Read CAS access to Rank 1UNC_M_RD_CAS_RANK2Read CAS access to Rank 2UNC_M_RD_CAS_RANK3Read CAS access to Rank 3UNC_M_RD_CAS_RANK4Read CAS access to Rank 4UNC_M_RD_CAS_RANK5Read CAS access to Rank 5UNC_M_RD_CAS_RANK6Read CAS access to Rank 6UNC_M_RD_CAS_RANK7Read CAS access to Rank 7UNC_M_VMSE_MXB_WR_OCCUPANCYUNC_M_VMSE_WR_PUSHVMSE WR push issuedUNC_M_WMM_TO_RMMUNC_M_WRONG_MMUNC_M_WR_CAS_RANK0Write CAS access to Rank 0UNC_M_WR_CAS_RANK1Write CAS access to Rank 1UNC_M_WR_CAS_RANK2Write CAS access to Rank 2UNC_M_WR_CAS_RANK3Write CAS access to Rank 3UNC_M_WR_CAS_RANK4Write CAS access to Rank 4UNC_M_WR_CAS_RANK5Write CAS access to Rank 5UNC_M_WR_CAS_RANK6Write CAS access to Rank 6UNC_M_WR_CAS_RANK7Write CAS access to Rank 7LOW_THRESSTARVEVMSE_RETRYVMSE write push issued in WMMVMSE write push issued in RMMBANK0BANK1BANK2BANK3BANK4BANK5BANK6BANK7ACTActivate due to readActivate due to writeBYPActivate due to bypassPrecharge due to readPrecharge due to writePrecharge due to bypassRD_RMMRD_WMMivbep_unc_pcuUNC_P_CORE8_TRANSITION_CYCLESUNC_P_CORE9_TRANSITION_CYCLESDeep C state rejection Core 0Deep C state rejection Core 1Deep C state rejection Core 2Deep C state rejection Core 3Deep C state rejection Core 4Deep C state rejection Core 5Deep C state rejection Core 6Deep C state rejection Core 7Deep C state rejection Core 8Deep C state rejection Core 9Core 0 C State DemotionsCore 1 C State DemotionsCore 2 C State DemotionsCore 3 C State DemotionsCore 4 C State DemotionsCore 5 C State DemotionsCore 6 C State DemotionsCore 7 C State DemotionsUNC_P_DEMOTIONS_CORE8Core 8 C State DemotionsUNC_P_DEMOTIONS_CORE9Core 9 C State DemotionsUNC_P_DEMOTIONS_CORE10Core 10 C State DemotionsUNC_P_DEMOTIONS_CORE11Core 11 C State DemotionsUNC_P_DEMOTIONS_CORE12Core 12 C State DemotionsUNC_P_DEMOTIONS_CORE13Core 13 C State DemotionsUNC_P_DEMOTIONS_CORE14Core 14 C State DemotionsUNC_P_PKG_C_EXIT_LATENCYivbep_unc_qpi2uncore_qpi_2ivbep_unc_qpi1ivbep_unc_qpi0VN1 Credit ConsumedVN_SHRfor shared VNFAILURE_RBT_HITSUCCESS_RBT_HITFAILURE_MISSFAILURE_CREDITS_MISSFAILURE_RBT_MISSFAILURE_CREDITS_RBT_MISSivbep_unc_uboUNC_U_PHOLD_CYCLESCycles PHOLD asserts to AckUNC_U_RACU_REQUESTSRACU requestsASSERT_TO_ACKACK_TO_DEASSERTivbep_unc_r2pcieUNC_R2_RXR_OCCUPANCYIngress occupancy accumulatorUNC_R2_RXR_INSERTSIngress insertsUNC_R2_TXR_NACK_CCWEgress counter-clockwise BACKUNC_R2_TXR_NACK_CWEgress clockwise BACKClockwiseCounter-clockwiseivbep_unc_r3qpi2uncore_r3qpi_2ivbep_unc_r3qpi1ivbep_unc_r3qpi0UNC_R3_RXR_AD_BYPASSEDVN0 Credit Acquisition FailedUNC_R3_C_HI_AD_CREDITS_EMPTYCbox AD credits emptyUNC_R3_C_LO_AD_CREDITS_EMPTYUNC_R3_HA_R2_BL_CREDITS_EMPTYHA/R2 AD credits  emptyUNC_R3_QPI0_AD_CREDITS_EMPTYQPI0 AD credits emptyUNC_R3_QPI0_BL_CREDITS_EMPTYQPI0 BL credits emptyUNC_R3_QPI1_AD_CREDITS_EMPTYQPI1 AD credits emptyUNC_R3_QPI1_BL_CREDITS_EMPTYQPI1 BL credits emptyUNC_R3_TXR_CYCLES_NEEgress cycles not emptyUNC_R3_TXR_NACK_CCWEgress NACK counter-clockwiseUNC_R3_TXR_NACK_CWUNC_R3_VN1_CREDITS_REJECTVN1 Credit Acquisition FailedUNC_R3_VN1_CREDITS_USEDFor AD ringFor BL ringAD clockwise Egress queueBL clockwise Egress queueVN0_HOMVN0 HOM messagesVN0_SNPVN0 SNP messagesVN0_NDRVN0 NDR messagesVN1_HOMVN1 HOM messagesVN1_SNPVN1 SNP messagesVN1_NDRVN1 NDR messagesHA0HA1R2_NCBR2 NCB messagesR2_NCSR2 NCS messagesCBO0CBox 0CBO1CBox 1CBO2CBox 2CBO3CBox 3CBO4CBox 4CBO5CBox 5CBO6CBox 6CBO7CBox 7CBO8CBox 8CBO9CBox 9CBO10CBox 10CBO11CBox 11CBO12CBox 12CBO13CBox 13CBO14CBox 14 & 16ivbep_unc_irpuncore_irpUNC_I_CLOCKTICKSUNC_I_ADDRESS_MATCHAddress match conflict countWrite ACK pending occupancyUNC_I_CACHE_OWN_OCCUPANCYUNC_I_CACHE_READ_OCCUPANCYOutstanding read occupancyUNC_I_CACHE_TOTAL_OCCUPANCYTotal write cache occupancyUNC_I_CACHE_WRITE_OCCUPANCYOutstanding write occupancyUNC_I_RXR_AK_CYCLES_FULLUNC_I_RXR_AK_INSERTSUNC_I_RXR_AK_OCCUPANCYUNC_I_RXR_BL_DRS_CYCLES_FULLUNC_I_RXR_BL_DRS_INSERTSBL Ingress occupancy DRSUNC_I_RXR_BL_DRS_OCCUPANCYUNC_I_RXR_BL_NCB_CYCLES_FULLUNC_I_RXR_BL_NCB_INSERTSBL Ingress occupancy NCBUNC_I_RXR_BL_NCB_OCCUPANCYUNC_I_RXR_BL_NCS_CYCLES_FULLUNC_I_RXR_BL_NCS_INSERTSBL Ingress Occupancy NCSUNC_I_RXR_BL_NCS_OCCUPANCYUNC_I_TICKLESTickle countUNC_I_TRANSACTIONSInbound transaction countNo AD Egress credit stallsNo BL Egress credit stallsUNC_I_TXR_DATA_INSERTS_NCBOutbound read requestsUNC_I_TXR_DATA_INSERTS_NCSUNC_I_TXR_REQUEST_OCCUPANCYWrite ordering stallsRD_PREFETCHESNumber of read prefetchesLOST_OWNERSHIPTOP_OF_QUEUEAny sourceMERGE_COUNThswep_unc_cbo17uncore_cbox_17hswep_unc_cbo16uncore_cbox_16hswep_unc_cbo15uncore_cbox_15hswep_unc_cbo14hswep_unc_cbo13hswep_unc_cbo12hswep_unc_cbo11hswep_unc_cbo10hswep_unc_cbo9hswep_unc_cbo8hswep_unc_cbo7hswep_unc_cbo6hswep_unc_cbo5hswep_unc_cbo4hswep_unc_cbo3hswep_unc_cbo2hswep_unc_cbo1hswep_unc_cbo0UNC_C_FAST_ASSERTEDUNC_C_BOUNCE_CONTROLBounce controlUNC_C_RXR_IPQ_RETRY2UNC_C_RXR_IRQ_RETRY2UNC_C_RXR_ISMQ_RETRY2UNC_C_SBO_CREDITS_ACQUIREDSBO credits acquiredUNC_C_SBO_CREDITS_OCCUPANCYSBO credits occupancyfor AD ringfor BL ringCVZERO_PREFETCH_VICTIMCVZERO_PREFETCH_MISSOPC_WILOPC_PCIWILOPC_PCIWIFAD_SBOBL_SBOPRQ_REJECTEDPRQ rejectedUp ring polarity filterDown ring polarity filterLines in F stateSTATE_DDebug cacheline stateSTATE_MPSTATE_MESIFDIntel Haswell-EP HA 1 uncorehswep_unc_ha1Intel Haswell-EP HA 0 uncorehswep_unc_ha0UNC_H_SNOOP_RESP_RECV_LOCALUNC_H_HITME_HITHits in the HitMe cacheUNC_H_HITME_HIT_PV_BITS_SETUNC_H_HITME_LOOKUPUNC_H_SBO0_CREDIT_ACQUIREDSBO0 credits acquiredUNC_H_SBO0_CREDIT_OCCUPANCYSBO0 credits occupancyUNC_H_SBO1_CREDIT_ACQUIREDSBO1 credits acquiredSBO1 credits occupancyUNC_H_SNOOPS_RSP_AFTER_DATAUNC_H_SNOOPS_CYCLES_NEUNC_H_SNOOPS_OCCUPANCYUNC_H_STALL_NO_SBO_CREDITStalls on no SBO creditsUNC_H_TRACKER_CYCLES_NETracker cycles not emptyUNC_H_TRACKER_OCCUPANCYTracker occupancy accumulatorUNC_H_TXR_STARVEDInjection starvationLocal read requestsRemote read requestsLocal write requestsRemote write requestsLocal InvItoE requestsRemote InvItoE requestsSBO0_ADNo credit for SBO0 AD RingSBO1_ADNo credit for SBO1 AD RingSBO0_BLNo credit for SBO0 BL RingSBO1_BLNo credit for SBO1 BL RingCancelled due to D2C or OtherREADS_LOCAL_USEFULLocal reads - usefulREMOTE_USEFULRemote - usefulChanel 3AD to QPI link 2BL to QPI link 2All requestsREAD_OR_INVITOEACKCNFLTWBIWBMTOE_OR_SRSPFWDI_REMOTERSPFWDI_LOCALRSPFWDSINVALSIntel Haswell-EP IMC7 uncorehswep_unc_imc7Intel Haswell-EP IMC6 uncorehswep_unc_imc6Intel Haswell-EP IMC5 uncorehswep_unc_imc5Intel Haswell-EP IMC4 uncorehswep_unc_imc4Intel Haswell-EP IMC3 uncorehswep_unc_imc3Intel Haswell-EP IMC2 uncorehswep_unc_imc2Intel Haswell-EP IMC1 uncorehswep_unc_imc1Intel Haswell-EP IMC0 uncorehswep_unc_imc0UNC_M_POWER_PCU_THROTTLINGPCU throttlingStarveVMSE retryBANK8BANK9BANK10BANK11BANK12BANK13BANK14BANK15ALLBANKSBANKG0Bank Group 0 (bank 0-3)BANKG1Bank Group 1 (bank 4-7)BANKG2Bank Group 2 (8-11)BANKG3Bank Group 3 (12-15)HighPanicIntel Haswell-EP PCU uncorehswep_unc_pcuUNC_P_DEMOTIONS_CORE15Core 15 C State DemotionsUNC_P_DEMOTIONS_CORE16Core 16 C State DemotionsUNC_P_DEMOTIONS_CORE17Core 17 C State DemotionsUNC_P_PKG_RESIDENCY_C0_CYCLESUNC_P_PKG_RESIDENCY_C3_CYCLESUNC_P_PKG_RESIDENCY_C6_CYCLESUNC_P_PKG_RESIDENCY_C7_CYCLESIntel Haswell-EP QPI1 uncorehswep_unc_qpi1Intel Haswell-EP QPI0 uncorehswep_unc_qpi0Intel Haswell-EP U-Box uncorehswep_unc_ubohswep_unc_r2pcieUNC_R2_SBO0_CREDITS_ACQUIREDUNC_R2_STALL_NO_SBO_CREDITStall on No SBo CreditsUNC_R2_IIO_CREDITFor SBO0, AD ringFor SBO1, AD ringFor SBO0, BL ringFor SBO1, BL ringDN_ADDN_BLDN_AKUP_ADUP_BLUP_AKAK clockwise Egress queuePRQ_QPI0PRQ_QPI1ISOCH_QPI0Isochronous QPI0ISOCH_QPI1Isochronous QPI1For ring ADFor ring BLhswep_unc_r3qpi2hswep_unc_r3qpi1hswep_unc_r3qpi0UNC_R3_RING_SINK_STARVEDR3 Ring stop starvedUNC_R3_RXR_CYCLES_NE_VN1VN1 Ingress Cycles Not EmptyUNC_R3_RXR_INSERTS_VN1VN1 Ingress AllocationsUNC_R3_RXR_OCCUPANCY_VN1UNC_R3_STALL_NO_SBO_CREDITStall no SBO creditQPI0 AD credits  emptyQPI0 BL credits  emptyUNC_R3_SBO0_CREDITS_ACQUIREDUNC_R3_SBO1_CREDITS_ACQUIREDEgress NACKFor AJ ringCBO14_16CBox 14 and CBox 16CBO15_17CBox 15 and CBox 17Intel Haswell-EP IRP uncorehswep_unc_irpUNC_I_SNOOP_RESPUNC_I_MISC0Miscellaneous eventsUNC_I_COHERENT_OPSCoherent operationsInbound transactionsUNC_I_MISC1Misc eventsRead prefetchesWR_PREFWrite prefetchesATOMICAtomic transactionsOther kinds of transactionsORDERINGQHit in Invalid stateHit in Modified stateSNPCODESnoop CodeSNPDATASnoop DataSNPINVSnoop InvalidSLOW_ISLOW_SSLOW_ESLOW_MLOST_FWDLOST forwardsSEC_RCVD_INVLDReceived InvalidSEC_RCVD_VLDReceived ValidDATA_THROTTLEData throttledFAST_REQFastpath requestsFAST_REJFastpath rejects2ND_RD_INSERT2ND_WR_INSERT2ND_ATOMIC_INSERTFAST_XFERPF_ACK_HINTPF_TIMEOUTPrefetch timeoutPCI read currentPCITOMDRITOMPCIDCAHINTCFLUSHhswep_unc_sbo3uncore_sbox_3hswep_unc_sbo2uncore_sbox_2hswep_unc_sbo1uncore_sbox_1hswep_unc_sbo0uncore_sbox_0UNC_S_CLOCKTICKSS-box Uncore clockticksUNC_S_RING_AD_USEDUNC_S_RING_AK_USEDUNC_S_RING_BL_USEDUNC_S_RING_IV_USEDUNC_S_RING_BOUNCESUNC_S_FAST_ASSERTEDUNC_S_RXR_OCCUPANCYUNC_S_RXR_BYPASSUNC_S_RXR_INSERTSUNC_S_TXR_ADS_USEDUNC_S_TXR_INSERTSUNC_S_TXR_OCCUPANCYAD credisAD_BNCAD bouncesBL_CRDBL creditsBL_BNCBL bouncesbdx_unc_cbo23uncore_cbox_23bdx_unc_cbo22uncore_cbox_22bdx_unc_cbo21uncore_cbox_21bdx_unc_cbo20uncore_cbox_20bdx_unc_cbo19uncore_cbox_19bdx_unc_cbo18uncore_cbox_18bdx_unc_cbo17bdx_unc_cbo16bdx_unc_cbo15bdx_unc_cbo14bdx_unc_cbo13bdx_unc_cbo12bdx_unc_cbo11bdx_unc_cbo10bdx_unc_cbo9bdx_unc_cbo8bdx_unc_cbo7bdx_unc_cbo6bdx_unc_cbo5bdx_unc_cbo4bdx_unc_cbo3bdx_unc_cbo2bdx_unc_cbo1bdx_unc_cbo0Clock ticksUNC_C_SBO_CREDIT_OCCUPANCYOnto AD RingOnto AK RingOnto BL RingLocal Memory - Opcode MatchedMisses to Local MemoryMiss Opcode MatchMisses to Remote MemoryNID MatchedNID Matched EvictionsNID Matched Miss AllNID and Opcode Matched MissNID and Opcode MatchedNID Matched WritebacksIngress Occupancy -- IPQIngress Occupancy -- IRQIRQ_REJPRQ_REJISMQ Retries -- Any RejectISMQ Retries -- ISMQ Retries -- No RTIDsIngress Allocations -- IPQIngress Allocations -- IRQIngress Allocations -- PRQBL Ring in Use -- AnyBL Ring in Use -- DownBL Ring in Use -- UpBL Ring in Use -- Up and EvenBL Ring in Use -- Up and OddAK Ring In Use -- AllAK Ring In Use -- DownAK Ring In Use -- UpAK Ring In Use -- Up and EvenAK Ring In Use -- Up and OddAD Ring In Use -- AllAD Ring In Use -- DownAD Ring In Use -- UpAD Ring In Use -- Up and EvenAD Ring In Use -- Up and OddCbo Misc -- RFO HitSCbo Misc -- Lines in Forward stateLines in S StateCache Lookups -- Any RequestIntel BroadwellX U-Box uncorebdx_unc_ubobdx_unc_sbo3bdx_unc_sbo2bdx_unc_sbo1bdx_unc_sbo0UNC_S_BOUNCE_CONTROLBypass the Sbo Ingress.UNC_S_TXR_ORDERINGTBIVSNOOPGO_UPIVSNOOP_DNAK_U2C_UP_EVENAK_U2C_UP_ODDAK_U2C_DN_EVENAK_U2C_DN_ODDEgress Occupancy -- AKEgress Occupancy -- IVEgress Allocations -- AKEgress Allocations -- IVIngress Occupancy -- AKIngress Occupancy -- IVIngress Allocations -- AKIngress Allocations -- IVBypass -- AD - BouncesBypass -- AD - CreditsBypass -- AKBypass -- BL - BouncesBypass -- BL - CreditsBypass -- IVDown and EventDown and OddIntel BroadwellX HA 1 uncorebdx_unc_ha1Intel BroadwellX HA 0 uncorebdx_unc_ha0UNC_H_SBO0_CREDITS_ACQUIREDUNC_H_SBO1_CREDITS_ACQUIREDUNC_H_SBO1_CREDIT_OCCUPANCYUNC_H_SNOOP_CYCLES_NEUNC_H_SNOOP_OCCUPANCYUNC_H_TRACKER_CYCLES_FULLScheduler 0Scheduler 1GPRSPxFWDxWBRSPxWBFor AD RingFor BL RingCounterclockwiseCounterclockwise and EvenCounterclockwise and OddClockwise and EvenClockwise and OddOSB Early Data Return -- AllOSB Snoop Broadcast -- RemoteHA to iMC Bypass -- Not TakenIntel BroadwellX IMC7 uncorebdx_unc_imc7Intel BroadwellX IMC6 uncorebdx_unc_imc6Intel BroadwellX IMC5 uncorebdx_unc_imc5Intel BroadwellX IMC4 uncorebdx_unc_imc4Intel BroadwellX IMC3 uncorebdx_unc_imc3Intel BroadwellX IMC2 uncorebdx_unc_imc2Intel BroadwellX IMC1 uncorebdx_unc_imc1Intel BroadwellX IMC0 uncorebdx_unc_imc0LOW_THRESHAccess to Rank 0 -- All BanksAccess to Rank 0 -- Bank 0Access to Rank 0 -- Bank 1Access to Rank 0 -- Bank 10Access to Rank 0 -- Bank 11Access to Rank 0 -- Bank 12Access to Rank 0 -- Bank 13Access to Rank 0 -- Bank 14Access to Rank 0 -- Bank 15Access to Rank 0 -- Bank 2Access to Rank 0 -- Bank 3Access to Rank 0 -- Bank 4Access to Rank 0 -- Bank 5Access to Rank 0 -- Bank 6Access to Rank 0 -- Bank 7Access to Rank 0 -- Bank 8Access to Rank 0 -- Bank 9Rank0 -- DIMM IDRank1 -- DIMM IDRank2 -- DIMM IDRank3 -- DIMM IDRank4 -- DIMM IDRank5 -- DIMM IDRank6 -- DIMM IDRank7 -- DIMM IDIntel BroadwellX IRP uncorebdx_unc_irpNumber of clocks in the IRP.Snoop Responses -- Hit E or SSnoop Responses -- Hit ISnoop Responses -- Hit MSnoop Responses -- MissSnoop Responses -- SnpCodeSnoop Responses -- SnpDataSnoop Responses -- SnpInvMisc Events - Set 1 -- Coherent Ops -- CLFlushCoherent Ops -- CRdCoherent Ops -- DRdCoherent Ops -- PCIDCAHin5tCoherent Ops -- PCIRdCurCoherent Ops -- PCIItoMCoherent Ops -- RFOCoherent Ops -- WbMtoIIntel BroadwellX PCU uncorebdx_unc_pcuUNC_P_UFS_BANDWIDTH_MAX_RANGEUNC_P_UFS_TRANSITIONS_DOWNUNC_P_UFS_TRANSITIONS_UP_RINGUNC_P_FIVR_PS_PS0_CYCLESUNC_P_FIVR_PS_PS1_CYCLESUNC_P_FIVR_PS_PS2_CYCLESUNC_P_FIVR_PS_PS3_CYCLESIntel BroadwellX QPI2 uncorebdx_unc_qpi2Intel BroadwellX QPI1 uncorebdx_unc_qpi1Intel BroadwellX QPI0 uncorebdx_unc_qpi0VN0 Credit Consumed -- DRSVN0 Credit Consumed -- HOMVN0 Credit Consumed -- NCBVN0 Credit Consumed -- NCSVN0 Credit Consumed -- NDRVN0 Credit Consumed -- SNPbdx_unc_r2pcieUNC_R2_RING_AK_BOUNCESEgress CCW NACK -- AD CCWEgress CCW NACK -- AK CCWEgress CCW NACK -- BL CCWEgress CCW NACK -- BL CWEgress Cycles Not Empty -- ADEgress Cycles Not Empty -- AKEgress Cycles Not Empty -- BLEgress Cycles Full -- ADEgress Cycles Full -- AKEgress Cycles Full -- BLAny directionsAK Ingress Bounced -- DnAK Ingress Bounced -- Upbdx_unc_r3qpi2bdx_unc_r3qpi1bdx_unc_r3qpi0Ingress Allocations -- DRSIngress Allocations -- HOMIngress Allocations -- NCBIngress Allocations -- NCSIngress Allocations -- NDRIngress Allocations -- SNPQPIx BL Credits EmptyVNA messagesHA/R2 AD Credits EmptyCBox AD Credits EmptyCBO_15_17Intel SkylakeX CHA27 uncoreskx_unc_cha27uncore_cha_27Intel SkylakeX CHA26 uncoreskx_unc_cha26uncore_cha_26Intel SkylakeX CHA25 uncoreskx_unc_cha25uncore_cha_25Intel SkylakeX CHA24 uncoreskx_unc_cha24uncore_cha_24Intel SkylakeX CHA23 uncoreskx_unc_cha23uncore_cha_23Intel SkylakeX CHA22 uncoreskx_unc_cha22uncore_cha_22Intel SkylakeX CHA21 uncoreskx_unc_cha21uncore_cha_21Intel SkylakeX CHA20 uncoreskx_unc_cha20uncore_cha_20Intel SkylakeX CHA19 uncoreskx_unc_cha19uncore_cha_19Intel SkylakeX CHA18 uncoreskx_unc_cha18uncore_cha_18Intel SkylakeX CHA17 uncoreskx_unc_cha17uncore_cha_17Intel SkylakeX CHA16 uncoreskx_unc_cha16uncore_cha_16Intel SkylakeX CHA15 uncoreskx_unc_cha15uncore_cha_15Intel SkylakeX CHA14 uncoreskx_unc_cha14uncore_cha_14Intel SkylakeX CHA13 uncoreskx_unc_cha13uncore_cha_13Intel SkylakeX CHA12 uncoreskx_unc_cha12uncore_cha_12Intel SkylakeX CHA11 uncoreskx_unc_cha11uncore_cha_11Intel SkylakeX CHA10 uncoreskx_unc_cha10uncore_cha_10Intel SkylakeX CHA9 uncoreskx_unc_cha9uncore_cha_9Intel SkylakeX CHA8 uncoreskx_unc_cha8uncore_cha_8Intel SkylakeX CHA7 uncoreskx_unc_cha7uncore_cha_7Intel SkylakeX CHA6 uncoreskx_unc_cha6uncore_cha_6Intel SkylakeX CHA5 uncoreskx_unc_cha5uncore_cha_5Intel SkylakeX CHA4 uncoreskx_unc_cha4uncore_cha_4Intel SkylakeX CHA3 uncoreskx_unc_cha3uncore_cha_3Intel SkylakeX CHA2 uncoreskx_unc_cha2uncore_cha_2Intel SkylakeX CHA1 uncoreskx_unc_cha1uncore_cha_1Intel SkylakeX CHA0 uncoreskx_unc_cha0uncore_cha_0UNC_C_AG0_AD_CRD_ACQUIREDUNC_C_AG0_AD_CRD_OCCUPANCYUNC_C_AG0_BL_CRD_ACQUIREDUNC_C_AG0_BL_CRD_OCCUPANCYUNC_C_AG1_AD_CRD_ACQUIREDUNC_C_AG1_AD_CRD_OCCUPANCYUNC_C_AG1_BL_CRD_OCCUPANCYUNC_C_AG1_BL_CREDITS_ACQUIREDUNC_C_BYPASS_CHA_IMCUNC_C_CMS_CLOCKTICKSUNC_C_CORE_PMAUNC_C_CORE_SNPUNC_C_DIR_LOOKUPUNC_C_DIR_UPDATEUNC_C_EGRESS_ORDERINGUNC_C_HITME_HITUNC_C_HITME_LOOKUPUNC_C_HITME_MISSUNC_C_HITME_UPDATEUNC_C_HORZ_RING_AD_IN_USEUNC_C_HORZ_RING_AK_IN_USEUNC_C_HORZ_RING_BL_IN_USEUNC_C_HORZ_RING_IV_IN_USEUNC_C_IMC_READS_COUNTUNC_C_IMC_WRITES_COUNTUNC_C_IODC_ALLOCUNC_C_IODC_DEALLOCUNC_C_OSBUNC_C_READ_NO_CREDITSUNC_C_REQUESTSUNC_C_RING_BOUNCES_HORZUNC_C_RING_BOUNCES_VERTUNC_C_RING_SINK_STARVED_HORZUNC_C_RING_SINK_STARVED_VERTUNC_C_RXC_INSERTSUNC_C_RXC_IPQ0_REJECTUNC_C_RXC_IPQ1_REJECTUNC_C_RXC_IRQ0_REJECTUNC_C_RXC_IRQ1_REJECTUNC_C_RXC_ISMQ0_REJECTUNC_C_RXC_ISMQ0_RETRYUNC_C_RXC_ISMQ1_REJECTUNC_C_RXC_ISMQ1_RETRYUNC_C_RXC_OCCUPANCYUNC_C_RXC_OTHER0_RETRYUNC_C_RXC_OTHER1_RETRYUNC_C_RXC_PRQ0_REJECTUNC_C_RXC_PRQ1_REJECTUNC_C_RXC_REQ_Q0_RETRYUNC_C_RXC_REQ_Q1_RETRYUNC_C_RXC_RRQ0_REJECTUNC_C_RXC_RRQ1_REJECTUNC_C_RXC_WBQ0_REJECTUNC_C_RXC_WBQ1_REJECTUNC_C_RXR_BUSY_STARVEDUNC_C_RXR_BYPASSUNC_C_RXR_CRD_STARVEDUNC_C_SF_EVICTIONUNC_C_SNOOPS_SENTUNC_C_SNOOP_RESPUNC_C_SNOOP_RESP_LOCALUNC_C_TXR_HORZ_ADS_USEDUNC_C_TXR_HORZ_BYPASSUNC_C_TXR_HORZ_CYCLES_FULLUNC_C_TXR_HORZ_CYCLES_NEUNC_C_TXR_HORZ_INSERTSUNC_C_TXR_HORZ_NACKUNC_C_TXR_HORZ_OCCUPANCYUNC_C_TXR_HORZ_STARVEDUNC_C_TXR_VERT_ADS_USEDUNC_C_TXR_VERT_BYPASSUNC_C_TXR_VERT_CYCLES_FULLUNC_C_TXR_VERT_CYCLES_NEUNC_C_TXR_VERT_INSERTSUNC_C_TXR_VERT_NACKUNC_C_TXR_VERT_OCCUPANCYUNC_C_TXR_VERT_STARVEDUNC_C_VERT_RING_AD_IN_USEUNC_C_VERT_RING_AK_IN_USEUNC_C_VERT_RING_BL_IN_USEUNC_C_VERT_RING_IV_IN_USEUNC_C_WB_PUSH_MTOIUNC_C_WRITE_NO_CREDITSUNC_C_XSNP_RESPANY_RSPI_FWDFEANY_RSPS_FWDFEANY_RSPS_FWDMANY_RSP_HITFSECORE_RSPI_FWDFECORE_RSPI_FWDMCORE_RSPS_FWDFECORE_RSPS_FWDMCORE_RSP_HITFSEEVICT_RSPI_FWDFEEVICT_RSPI_FWDMEVICT_RSPS_FWDFEEVICT_RSPS_FWDMEVICT_RSP_HITFSEEXT_RSPI_FWDFEEXT_RSPI_FWDMEXT_RSPS_FWDFEEXT_RSPS_FWDMEXT_RSP_HITFSEEDC0_SMI2EDC1_SMI3EDC2_SMI4EDC3_SMI5MC0_SMI0MC1_SMI1WbPushMtoI -- Pushed to LLCVertical IV Ring in Use -- UpAD_AG0AD_AG1AK_AG0AK_AG1BL_AG0BL_AG1CMS Vertical ADS Used -- IVAK_BNCIV_BNCALL_HITIA_HITIA_MISSIO_HITIO_MISSTOR Occupancy -- MissTOR Occupancy -- IPQTOR Occupancy -- IRQTOR Occupancy -- PRQOPC0_SNP_CUROPC0_SNP_CODEOPC0_SNP_DATAOPC0_SNP_DATA_MIGOPC0_SNP_INV_OWNOPC0_SNP_INVOPC1_SNP_CUROPC1_SNP_CODEOPC1_SNP_DATAOPC1_SNP_DATA_MIGOPC1_SNP_INV_OWNOPC1_SNP_INVOPC0_RFOOPC0_CRDIRQ Opcode: Demand code readOPC0_DRDOPC0_PRDOPC0_WCILFOPC0_WCILOPC0_UCRDFOPC0_WILOPC0_WB_PUSH_HINTIRQ Opcode: TBDOPC0_WB_MTOIOPC0_WB_MTOEOPC0_WB_EFTOIOPC0_WB_EFTOEOPC0_ITOMOPC0_LLC_PF_RFOOPC0_LLC_PF_CODEOPC0_LLC_PF_DATAOPC0_INT_LOGOPC0_INT_PHYOPC0_PRI_UPOPC0_SPLIT_LOCKOPC0_LOCKOPC1_RFOOPC1_CRDOPC1_DRDOPC1_PRDOPC1_WCILFOPC1_WCILOPC1_UCRDFOPC1_WILOPC1_WB_PUSH_HINTOPC1_WB_MTOIOPC1_WB_MTOEOPC1_WB_EFTOIOPC1_WB_EFTOEOPC1_ITOMOPC1_LLC_PF_RFOOPC1_LLC_PF_CODEOPC1_LLC_PF_DATAOPC1_INT_LOGOPC1_INT_PHYOPC1_PRI_UPOPC1_SPLIT_LOCKOPC1_LOCKOPC0_RD_CUROPC0_RD_CODEOPC0_RD_DATAOPC0_RD_DATA_MIGOPC0_RD_INV_OWNOPC0_RD_INV_XTOIOPC0_RD_PUSH_HINTPRQ Opcode: Read push hintOPC0_RD_INV_ITOEOPC0_RD_INVOPC0_RD_INV_ITOMOPC1_RD_CUROPC1_RD_CODEOPC1_RD_DATAOPC1_RD_DATA_MIGOPC1_RD_INV_OWNOPC1_RD_INV_XTOIOPC1_RD_PUSH_HINTOPC1_RD_INV_ITOEOPC1_RD_INVOPC1_RD_INV_ITOMALL_IO_IATOR Inserts -- MissTOR Inserts -- IPQTOR Inserts -- IRQTOR Inserts -- PRQTGR0TGR1TGR2TGR3TGR4TGR5RSPFWDRSPCNFLCTSRSP_WBWBSnoops Sent -- AllBCST_LOCALBCST_REMOTEDIRECT_LOCALDIRECT_REMOTEIFVALLOW_SNPWBQ Rejects -- Allow SnoopWBQ Rejects -- ANY0WBQ Rejects -- HALLC_OR_SF_WAYLLC_VICTIMWBQ Rejects -- LLC VictimPA_MATCHWBQ Rejects -- PhyAddr MatchSF_VICTIMWBQ Rejects -- SF VictimWBQ Rejects -- VictimWBQ Rejects -- AD REQ on VN0AD_RSP_VN0WBQ Rejects -- AD RSP on VN0AK_NON_UPIBL_NCB_VN0WBQ Rejects -- BL NCB on VN0BL_NCS_VN0WBQ Rejects -- BL NCS on VN0BL_RSP_VN0WBQ Rejects -- BL RSP on VN0BL_WB_VN0WBQ Rejects -- BL WB on VN0IV_NON_UPIRRQ Rejects -- Allow SnoopRRQ Rejects -- ANY0RRQ Rejects -- HARRQ Rejects -- LLC VictimRRQ Rejects -- PhyAddr MatchRRQ Rejects -- SF VictimRRQ Rejects -- VictimRRQ Rejects -- AD REQ on VN0RRQ Rejects -- AD RSP on VN0RRQ Rejects -- BL NCB on VN0RRQ Rejects -- BL NCS on VN0RRQ Rejects -- BL RSP on VN0RRQ Rejects -- BL WB on VN0Request Queue Retries -- ANY0Request Queue Retries -- HAOther Retries -- Allow SnoopOther Retries -- ANY0Other Retries -- HAOther Retries -- LLC VictimOther Retries -- SF VictimOther Retries -- VictimOther Retries -- BL WB on VN0RRQWBQISMQ Retries -- ANY0ISMQ Retries -- HAISMQ Rejects -- ANY0ISMQ Rejects -- HAISMQ Retries -- AD REQ on VN0ISMQ Retries -- AD RSP on VN0ISMQ Retries -- BL NCB on VN0ISMQ Retries -- BL NCS on VN0ISMQ Retries -- BL RSP on VN0ISMQ Retries -- BL WB on VN0ISMQ Rejects -- AD REQ on VN0ISMQ Rejects -- AD RSP on VN0ISMQ Rejects -- BL NCB on VN0ISMQ Rejects -- BL NCS on VN0ISMQ Rejects -- BL RSP on VN0ISMQ Rejects -- BL WB on VN0CV0_PREF_MISSCbo Misc -- CV0 Prefetch MissCV0_PREF_VICLOCAL_ALLLOCAL_ELOCAL_MREMOTE_ALLREMOTE_EREMOTE_MTOTAL_ETOTAL_FTOTAL_MTOTAL_SSTATE_LLC_ILLC Invalid cacheline stateSTATE_SF_SSF Shared cacheline stateSTATE_SF_ESF Exclusive cacheline stateSTATE_SF_HSF H cacheline stateSTATE_LLC_SLLC Shared cacheline stateSTATE_LLC_ELLC Exclusive cacheline stateSTATE_LLC_MLLC Modified cacheline stateSTATE_LLC_FLLC Forward cacheline stateSTATE_CACHE_ANYSNPOUTWBPUSHMTOIINVITOMIODCFULLOSBGATEDFULL_MIGFULL_PRIORITYPARTIAL_MIGPARTIAL_PRIORITYLEFTRIGHTLEFT_EVENLEFT_ODDRIGHT_EVENRIGHT_ODDDEALLOCATEDEALLOCATE_RSPFWDI_LOCRSPFWDI_REMNOTSHARED_RDINVOWNREAD_OR_INVEX_RDSSHARED_OWNREQWBMTOI_OR_SIV_SNOOPGO_DNIV_SNOOPGO_UPANY_GTONEANY_ONEANY_REMOTECORE_GTONECORE_ONEEVICT_GTONEEVICT_ONEEVICT_REMOTEEXT_GTONEEXT_ONEEXT_REMOTEC1_STATECore PMA Events -- C1  StateC1_TRANSITIONC6_STATECore PMA Events -- C6 StateC6_TRANSITIONCore PMA Events -- GVINTERMEDIATECHA to iMC Bypass -- TakenIntel SkylakeX IIO5 uncoreskx_unc_iio5uncore_iio_5Intel SkylakeX IIO4 uncoreskx_unc_iio4uncore_iio_4Intel SkylakeX IIO3 uncoreskx_unc_iio3uncore_iio_3Intel SkylakeX IIO2 uncoreskx_unc_iio2uncore_iio_2Intel SkylakeX IIO1 uncoreskx_unc_iio1uncore_iio_1Intel SkylakeX IIO0 uncoreskx_unc_iio0uncore_iio_0UNC_IO_CLOCKTICKSIIO clockticksUNC_IO_COMP_BUF_INSERTSUNC_IO_COMP_BUF_OCCUPANCYUNC_IO_DATA_REQ_BY_CPUUNC_IO_DATA_REQ_OF_CPUUNC_IO_LINK_NUM_CORR_ERRUNC_IO_LINK_NUM_RETRIESUNC_IO_MASK_MATCHUNC_IO_MASK_MATCH_ANDUNC_IO_MASK_MATCH_ORUNC_IO_NOTHINGUNC_IO_SYMBOL_TIMESUNC_IO_TXN_REQ_BY_CPUUNC_IO_TXN_REQ_OF_CPUUNC_IO_VTD_ACCESSUNC_IO_VTD_OCCUPANCYCTXT_MISSVTd Access -- L1 missVTd Access -- L2 missVTd Access -- L3 missL4_PAGE_HITVTd Access -- Vtd hitTLB1_MISSVTd Access -- TLB missTLB_FULLVTd Access -- TLB is fullBUS0NOT_BUS0_BUS1NOT_BUS0_NOT_BUS1ATOMIC_PART0ATOMIC_PART1ATOMIC_PART2ATOMIC_PART3ATOMIC_VTD0ATOMIC_VTD1ATOMICCMP_PART0ATOMICCMP_PART1ATOMICCMP_PART2ATOMICCMP_PART3MEM_READ_PART0MEM_READ_PART1MEM_READ_PART2MEM_READ_PART3MEM_READ_VTD0MEM_READ_VTD1MEM_READ_ANYMEM_WRITE_PART0MEM_WRITE_PART1MEM_WRITE_PART2MEM_WRITE_PART3MEM_WRITE_VTD0MEM_WRITE_VTD1MSG_PART0MSG_PART1MSG_PART2MSG_PART3MSG_VTD0MSG_VTD1PEER_READ_PART0PEER_READ_PART1PEER_READ_PART2PEER_READ_PART3PEER_READ_VTD0PEER_READ_VTD1PEER_WRITE_PART0PEER_WRITE_PART1PEER_WRITE_PART2PEER_WRITE_PART3PEER_WRITE_VTD0PEER_WRITE_VTD1FC_POSTED_REQFC_NON_POSTED_REQNon-Posted requestsFC_CMPLCompletion requestsFC_ANYAny type of requestsCFG_READ_PART0CFG_READ_PART1CFG_READ_PART2CFG_READ_PART3CFG_READ_VTD0CFG_READ_VTD1CFG_WRITE_PART0CFG_WRITE_PART1CFG_WRITE_PART2CFG_WRITE_PART3CFG_WRITE_VTD0CFG_WRITE_VTD1IO_READ_PART0IO_READ_PART1IO_READ_PART2IO_READ_PART3IO_READ_VTD0IO_READ_VTD1IO_WRITE_PART0IO_WRITE_PART1IO_WRITE_PART2IO_WRITE_PART3IO_WRITE_VTD0IO_WRITE_VTD1MEM_WRITE_ANYPEER_READ_ANYPEER_WRITE_ANYPORT2ANY_PORTPORT0:PORT1:PORT2:PORT3Intel SkylakeX IMC5 uncoreskx_unc_imc5Intel SkylakeX IMC4 uncoreskx_unc_imc4Intel SkylakeX IMC3 uncoreskx_unc_imc3Intel SkylakeX IMC2 uncoreskx_unc_imc2Intel SkylakeX IMC1 uncoreskx_unc_imc1Intel SkylakeX IMC0 uncoreskx_unc_imc0Read Cass Access to RankWrite VAS to RankAccess to all banksAccess to Bank 0Access to Bank 1Access to Bank 2Access to Bank 3Access to Bank 4Access to Bank 5Access to Bank 6Access to Bank 7Access to Bank 8Access to Bank 9Access to Bank 10Access to Bank 11Access to Bank 12Access to Bank 13Access to Bank 14Access to Bank 15RD_ISOCHWR_ISOCHIntel SkylakeX IRP uncoreskx_unc_irpIRP ClocksUNC_I_FAF_FULLUNC_I_FAF_INSERTSUNC_I_FAF_OCCUPANCYUNC_I_FAF_TRANSACTIONSUNC_I_IRP_ALLUNC_I_P2P_INSERTSP2P requests from the ITCUNC_I_P2P_OCCUPANCYP2P B & S Queue OccupancyUNC_I_P2P_TRANSACTIONSUNC_I_TXC_AK_INSERTSUNC_I_TXC_BL_DRS_CYCLES_FULLUNC_I_TXC_BL_DRS_INSERTSUNC_I_TXC_BL_DRS_OCCUPANCYUNC_I_TXC_BL_NCB_CYCLES_FULLUNC_I_TXC_BL_NCB_INSERTSUNC_I_TXC_BL_NCB_OCCUPANCYUNC_I_TXC_BL_NCS_CYCLES_FULLUNC_I_TXC_BL_NCS_INSERTSUNC_I_TXC_BL_NCS_OCCUPANCYUNC_I_TXS_DATA_INSERTS_NCBUNC_I_TXS_DATA_INSERTS_NCSUNC_I_TXS_REQUEST_OCCUPANCYLOC_AND_TGT_MATCHP2P Transactions -- P2P readsREM_AND_TGT_MATCHMisc Events - Set 0 -- INBOUND_INSERTSOUTBOUND_INSERTSIV_QIntel SkylakeX M2M1 uncoreskx_unc_m2m1uncore_m2m_1Intel SkylakeX M2M0 uncoreskx_unc_m2m0uncore_m2m_0UNC_M2_AG0_AD_CRD_ACQUIREDUNC_M2_AG0_AD_CRD_OCCUPANCYUNC_M2_AG0_BL_CRD_ACQUIREDUNC_M2_AG0_BL_CRD_OCCUPANCYUNC_M2_AG1_AD_CRD_ACQUIREDUNC_M2_AG1_AD_CRD_OCCUPANCYUNC_M2_AG1_BL_CRD_OCCUPANCYUNC_M2_BYPASS_M2M_EGRESSUNC_M2_BYPASS_M2M_INGRESSUNC_M2_CLOCKTICKSUNC_M2_CMS_CLOCKTICKSUNC_M2_DIRECT2CORE_TAKENUNC_M2_DIRECT2UPI_TAKENUNC_M2_DIRECTORY_HITUNC_M2_DIRECTORY_LOOKUPUNC_M2_DIRECTORY_MISSUNC_M2_DIRECTORY_UPDATEUNC_M2_EGRESS_ORDERINGUNC_M2_FAST_ASSERTEDUNC_M2_HORZ_RING_AD_IN_USEUNC_M2_HORZ_RING_AK_IN_USEUNC_M2_HORZ_RING_BL_IN_USEUNC_M2_HORZ_RING_IV_IN_USEUNC_M2_IMC_READSUNC_M2_IMC_WRITESUNC_M2_PKT_MATCHUNC_M2_PREFCAM_CYCLES_FULLUNC_M2_PREFCAM_CYCLES_NEUNC_M2_PREFCAM_INSERTSUNC_M2_PREFCAM_OCCUPANCYUNC_M2_RING_BOUNCES_HORZUNC_M2_RING_BOUNCES_VERTUNC_M2_RING_SINK_STARVED_HORZUNC_M2_RING_SINK_STARVED_VERTUNC_M2_RING_SRC_THRTLUNC_M2_RPQ_CYCLES_REG_CREDITSUNC_M2_RXC_AD_CYCLES_FULLUNC_M2_RXC_AD_CYCLES_NEUNC_M2_RXC_AD_INSERTSUNC_M2_RXC_AD_OCCUPANCYUNC_M2_RXC_BL_CYCLES_FULLUNC_M2_RXC_BL_CYCLES_NEUNC_M2_RXC_BL_INSERTSUNC_M2_RXC_BL_OCCUPANCYUNC_M2_RXR_BUSY_STARVEDUNC_M2_RXR_BYPASSUNC_M2_RXR_CRD_STARVEDUNC_M2_RXR_INSERTSUNC_M2_RXR_OCCUPANCYUNC_M2_TGR_AD_CREDITSUNC_M2_TGR_BL_CREDITSUNC_M2_TRACKER_CYCLES_FULLUNC_M2_TRACKER_CYCLES_NEUNC_M2_TRACKER_INSERTSUNC_M2_TRACKER_OCCUPANCYUNC_M2_TXC_AD_CYCLES_FULLUNC_M2_TXC_AD_CYCLES_NEUNC_M2_TXC_AD_INSERTSUNC_M2_TXC_AD_OCCUPANCYUNC_M2_TXC_AKUNC_M2_TXC_AK_CYCLES_FULLUNC_M2_TXC_AK_CYCLES_NEUNC_M2_TXC_AK_INSERTSUNC_M2_TXC_AK_OCCUPANCYUNC_M2_TXC_AK_SIDEBANDUNC_M2_TXC_BLUNC_M2_TXC_BL_CYCLES_FULLUNC_M2_TXC_BL_CYCLES_NEUNC_M2_TXC_BL_INSERTSUNC_M2_TXC_BL_OCCUPANCYUNC_M2_TXR_HORZ_ADS_USEDUNC_M2_TXR_HORZ_BYPASSUNC_M2_TXR_HORZ_CYCLES_FULLUNC_M2_TXR_HORZ_CYCLES_NEUNC_M2_TXR_HORZ_INSERTSUNC_M2_TXR_HORZ_NACKUNC_M2_TXR_HORZ_OCCUPANCYUNC_M2_TXR_HORZ_STARVEDUNC_M2_TXR_VERT_ADS_USEDUNC_M2_TXR_VERT_BYPASSUNC_M2_TXR_VERT_CYCLES_FULLUNC_M2_TXR_VERT_CYCLES_NEUNC_M2_TXR_VERT_INSERTSUNC_M2_TXR_VERT_NACKUNC_M2_TXR_VERT_OCCUPANCYUNC_M2_TXR_VERT_STARVEDUNC_M2_VERT_RING_AD_IN_USEUNC_M2_VERT_RING_AK_IN_USEUNC_M2_VERT_RING_BL_IN_USEUNC_M2_VERT_RING_IV_IN_USEUNC_M2_WPQ_CYCLES_REG_CREDITSUNC_M2_WRITE_TRACKER_INSERTSCMS0CMS1DRS_UPIRDCRDWRCMPWRCRDPREF_RD_CAM_HITRDCRD0RDCRD1WRCMP0WRCMP1WRCRD0WRCRD1Tracker Inserts -- Channel 0Tracker Inserts -- Channel 1Tracker Inserts -- Channel 2MESHFROM_TRANSGRESSDirectory Updates -- A2IDirectory Updates -- A2SDirectory Updates -- AnyDirectory Updates -- I2ADirectory Updates -- I2SDirectory Updates -- S2ADirectory Updates -- S2ICLEAN_ACLEAN_ICLEAN_PCLEAN_SDIRTY_ADIRTY_IDIRTY_PDIRTY_SSTATE_ADirectory Lookups -- A StateDirectory Lookups -- I StateDirectory Lookups -- S StateM2M to iMC Bypass -- TakenIntel SkylakeX M3UPI2 uncoreskx_unc_m3upi2uncore_m3upi_2Intel SkylakeX M3UPI1 uncoreskx_unc_m3upi1uncore_m3upi_1Intel SkylakeX M3UPI0 uncoreskx_unc_m3upi0uncore_m3upi_0UNC_M3_AG0_AD_CRD_ACQUIREDUNC_M3_AG0_AD_CRD_OCCUPANCYUNC_M3_AG0_BL_CRD_ACQUIREDUNC_M3_AG0_BL_CRD_OCCUPANCYUNC_M3_AG1_AD_CRD_ACQUIREDUNC_M3_AG1_AD_CRD_OCCUPANCYUNC_M3_AG1_BL_CRD_OCCUPANCYUNC_M3_CHA_AD_CREDITS_EMPTYUNC_M3_CLOCKTICKSUNC_M3_CMS_CLOCKTICKSUNC_M3_D2C_SENTUNC_M3_D2U_SENTUNC_M3_EGRESS_ORDERINGUNC_M3_FAST_ASSERTEDUNC_M3_HORZ_RING_AD_IN_USEUNC_M3_HORZ_RING_AK_IN_USEUNC_M3_HORZ_RING_BL_IN_USEUNC_M3_HORZ_RING_IV_IN_USEUNC_M3_M2_BL_CREDITS_EMPTYUNC_M3_MULTI_SLOT_RCVDUNC_M3_RING_BOUNCES_HORZUNC_M3_RING_BOUNCES_VERTUNC_M3_RING_SINK_STARVED_HORZUNC_M3_RING_SINK_STARVED_VERTUNC_M3_RING_SRC_THRTLUNC_M3_RXC_ARB_LOST_VN0UNC_M3_RXC_ARB_LOST_VN1UNC_M3_RXC_ARB_MISCUNC_M3_RXC_ARB_NOAD_REQ_VN0UNC_M3_RXC_ARB_NOAD_REQ_VN1UNC_M3_RXC_ARB_NOCRED_VN0UNC_M3_RXC_ARB_NOCRED_VN1UNC_M3_RXC_BYPASSEDUNC_M3_RXC_COLLISION_VN0UNC_M3_RXC_COLLISION_VN1UNC_M3_RXC_CRD_MISCUNC_M3_RXC_CRD_OCCUNC_M3_RXC_CYCLES_NE_VN0UNC_M3_RXC_CYCLES_NE_VN1UNC_M3_RXC_FLITS_GEN_BLUNC_M3_RXC_FLITS_MISCUNC_M3_RXC_FLITS_SENTUNC_M3_RXC_FLITS_SLOT_BLUNC_M3_RXC_FLIT_GEN_HDR1UNC_M3_RXC_FLIT_GEN_HDR2UNC_M3_RXC_FLIT_NOT_SENTUNC_M3_RXC_HELDUNC_M3_RXC_INSERTS_VN0UNC_M3_RXC_INSERTS_VN1UNC_M3_RXC_OCCUPANCY_VN0UNC_M3_RXC_OCCUPANCY_VN1UNC_M3_RXC_PACKING_MISS_VN0UNC_M3_RXC_PACKING_MISS_VN1UNC_M3_RXC_SMI3_PFTCHUNC_M3_RXC_VNA_CRDUNC_M3_RXR_BUSY_STARVEDUNC_M3_RXR_BYPASSUNC_M3_RXR_CRD_STARVEDUNC_M3_RXR_INSERTSUNC_M3_RXR_OCCUPANCYUNC_M3_TXC_AD_ARB_FAILUNC_M3_TXC_AD_FLQ_BYPASSUNC_M3_TXC_AD_FLQ_CYCLES_NEUNC_M3_TXC_AD_FLQ_INSERTSUNC_M3_TXC_AD_FLQ_OCCUPANCYUNC_M3_TXC_AD_SNPF_GRP1_VN1UNC_M3_TXC_AD_SNPF_GRP2_VN1UNC_M3_TXC_AK_FLQ_INSERTSUNC_M3_TXC_AK_FLQ_OCCUPANCYUNC_M3_TXC_BL_ARB_FAILUNC_M3_TXC_BL_FLQ_CYCLES_NEUNC_M3_TXC_BL_FLQ_INSERTSUNC_M3_TXC_BL_FLQ_OCCUPANCYUNC_M3_TXR_HORZ_ADS_USEDUNC_M3_TXR_HORZ_BYPASSUNC_M3_TXR_HORZ_CYCLES_FULLUNC_M3_TXR_HORZ_CYCLES_NEUNC_M3_TXR_HORZ_INSERTSUNC_M3_TXR_HORZ_NACKUNC_M3_TXR_HORZ_OCCUPANCYUNC_M3_TXR_HORZ_STARVEDUNC_M3_TXR_VERT_ADS_USEDUNC_M3_TXR_VERT_BYPASSUNC_M3_TXR_VERT_CYCLES_FULLUNC_M3_TXR_VERT_CYCLES_NEUNC_M3_TXR_VERT_INSERTSUNC_M3_TXR_VERT_NACKUNC_M3_TXR_VERT_OCCUPANCYUNC_M3_TXR_VERT_STARVEDUNC_M3_UPI_PREFETCH_SPAWNUNC_M3_VERT_RING_AD_IN_USEUNC_M3_VERT_RING_AK_IN_USEUNC_M3_VERT_RING_BL_IN_USEUNC_M3_VERT_RING_IV_IN_USEUNC_M3_VN0_CREDITS_USEDUNC_M3_VN0_NO_CREDITSUNC_M3_VN1_CREDITS_USEDUNC_M3_VN1_NO_CREDITSVN1 No Credits -- WB on BLVN1 No Credits -- NCB on BLVN1 No Credits -- REQ on ADVN1 No Credits -- RSP on ADVN1 No Credits -- SNP on ADVN1 No Credits -- RSP on BLVN1 Credit Used -- WB on BLVN1 Credit Used -- NCB on BLVN1 Credit Used -- REQ on ADVN1 Credit Used -- RSP on ADVN1 Credit Used -- SNP on ADVN1 Credit Used -- RSP on BLVN0 No Credits -- WB on BLVN0 No Credits -- NCB on BLVN0 No Credits -- REQ on ADVN0 No Credits -- RSP on ADVN0 No Credits -- SNP on ADVN0 No Credits -- RSP on BLVN0 Credit Used -- WB on BLVN0 Credit Used -- NCB on BLVN0 Credit Used -- REQ on ADVN0 Credit Used -- RSP on ADVN0 Credit Used -- SNP on ADVN0 Credit Used -- RSP on BLVN0_NCS_NCBVN0_RSPVN0_WBVN1_NCS_NCBVN1_RSPVN1_WBUPI0 BL Credits Empty -- VNAVN0_REQVN1_REQUPI0 AD Credits Empty -- VNAVN1_NCBVN1_NCSVN0_SNPFP_NONSNPVN0_SNPFP_VN2SNPVN1_SNPFP_NONSNPVN1_SNPFP_VN0SNPVN0_CHAVN0_NON_IDLEVN0_PEER_UPI0VN0_PEER_UPI1VN1_CHAVN1_NON_IDLEVN1_PEER_UPI0VN1_PEER_UPI1AD_SLOT0AD FlowQ Bypass -- AD_SLOT1AD_SLOT2BL_EARLY_RSPANY_IN_USECORRECTEDLT1LT4LT5Remote VNA Credits -- UsedARB_LOSTDROP_OLDDROP_WRAPSLOTTEDAD_REQAD_RSPAD_SNPBL_NCBBL_NCSBL_RSPBL_WBCANT_SLOT_ADMessage Held -- Cant Slot AADCANT_SLOT_BLMessage Held -- Cant Slot BBLPARALLEL_AD_LOSTPARALLEL_ATTEMPTPARALLEL_BL_LOSTPARALLEL_SUCCESSMessage Held -- VN0Message Held -- VN1Header Not Sent -- AllNO_BGF_CRDNO_BGF_NO_MSGNO_TXQ_CRDNO_TXQ_NO_MSGONE_TAKENTHREE_TAKENTWO_TAKENRMSTALLRMSTALL_NOMSGACCUMACCUM_READACCUM_WASTEDAHEAD_BLOCKEDAHEAD_MSGPARPAR_FLITPAR_MSGNEED_DATAP0_WAITP1_NOT_REQP1_NOT_REQ_BUT_BUBBLEP1_NOT_REQ_NOT_AVAILP1_WAIT1_MSG1_MSG_VNX2_MSGS3_MSGSSLOTS_1Sent Header Flit -- SLOTS_2SLOTS_3P1P_AT_LIMITP1P_BUSYP1P_FIFO_FULLP1P_HOLD_P0P1P_TO_LIMBOData Flit Not Sent -- AllNO_BGFNO_TXQD2K_CRDFLITS_IN_FIFOFLITS_IN_PATHP1P_FIFOCredit Occupancy -- P1P_TOTALTxQ_CRDVNA_IN_USEANY_BGF_FIFOANY_BGF_PATHAD_S0_BL_ARBAD_S0_IDLEAD_S1_BL_SLOTAD_S2_BL_SLOTCant Arb for VN1 -- WB on BBLCant Arb for VN0 -- WB on BBLADBL_PARALLEL_WINNO_PROG_AD_VN0NO_PROG_AD_VN1NO_PROG_BL_VN0NO_PROG_BL_VN1PAR_BIAS_VN0PAR_BIAS_VN1Lost Arb for VN1 -- REQ on ADLost Arb for VN1 -- RSP on ADLost Arb for VN1 -- SNP on ADLost Arb for VN1 -- NCB on BLLost Arb for VN1 -- NCS on BLLost Arb for VN1 -- RSP on BLLost Arb for VN1 -- WB on BLLost Arb for VN0 -- REQ on ADLost Arb for VN0 -- RSP on ADLost Arb for VN0 -- SNP on ADLost Arb for VN0 -- NCB on BLLost Arb for VN0 -- NCS on BLLost Arb for VN0 -- RSP on BLLost Arb for VN0 -- WB on BLAK_SLOT0AK_SLOT2BL_SLOT0IIO0_IIO1_NCBIIO2_NCBM2 BL Credits Empty -- IIO2IIO3_NCBM2 BL Credits Empty -- IIO3IIO4_NCBM2 BL Credits Empty -- IIO4IIO5_NCBM2 BL Credits Empty -- IIO5NCS_SELIntel SkylakeX PCU uncoreskx_unc_pcuUNC_P_CORE_TRANSITION_CYCLESUNC_P_CTS_EVENT0UNC_P_CTS_EVENT1UNC_P_DEMOTIONSUNC_P_MCP_PROCHOT_CYCLESUNC_P_PMAX_THROTTLED_CYCLESIntel SkylakeX U-Box uncoreskx_unc_uboPHOLD cycles.UNC_U_RACU_DRNGPFTCH_BUF_EMPTYRDRANDRDSEEDMessage Received -- Message Received -- IPIMessage Received -- MSIMessage Received -- VLWIntel SkylakeX UPI2 uncoreskx_unc_upi2uncore_upi_2Intel SkylakeX UPI1 uncoreskx_unc_upi1uncore_upi_1Intel SkylakeX UPI0 uncoreskx_unc_upi0uncore_upi_0UNC_UPI_CLOCKTICKSUNC_UPI_DIRECT_ATTEMPTSUNC_UPI_FLOWQ_NO_VNA_CRDUNC_UPI_L1_POWER_CYCLESUNC_UPI_M3_BYP_BLOCKEDUNC_UPI_M3_CRD_RETURN_BLOCKEDUNC_UPI_M3_RXQ_BLOCKEDUNC_UPI_PHY_INIT_CYCLESUNC_UPI_POWER_L1_NACKUNC_UPI_POWER_L1_REQUNC_UPI_REQ_SLOT2_FROM_M3UNC_UPI_RXL0P_POWER_CYCLESUNC_UPI_RXL0_POWER_CYCLESUNC_UPI_RXL_BASIC_HDR_MATCHUNC_UPI_RXL_BYPASSEDUNC_UPI_RXL_FLITSUNC_UPI_RXL_INSERTSUNC_UPI_RXL_OCCUPANCYUNC_UPI_RXL_SLOT_BYPASSUNC_UPI_TXL0P_CLK_ACTIVEUNC_UPI_TXL0P_POWER_CYCLESUNC_UPI_TXL0_POWER_CYCLESUNC_UPI_TXL_BASIC_HDR_MATCHUNC_UPI_TXL_BYPASSEDUNC_UPI_TXL_FLITSUNC_UPI_TXL_INSERTSUNC_UPI_TXL_OCCUPANCYALL_DATAValid Flits Sent -- All DataALL_NULLValid Flits Sent -- DataValid Flits Sent -- IdleValid Flits Sent -- LLCTRLValid Flits Sent -- Slot 0Valid Flits Sent -- Slot 1Valid Flits Sent -- Slot 2CFG_CTLDFXRXQRXQ_BYPASSRXQ_CREDSPARES0_RXQ1S0_RXQ2S1_RXQ0S1_RXQ2S2_RXQ0S2_RXQ1Valid Flits Received -- DataValid Flits Received -- IdleNCB_OPC_NCWRNCB_OPC_WCWRNCB_OPC_NCMSGBNCB_OPC_INTLOGICALNCB_OPC_INTPHYSICALNCB_OPC_INTPRIOUPDNCB_OPC_NCWRPTLNCB_OPC_NCP2PBNCS_OPC_NCRDNCS_OPC_INTACKNCS_OPC_NCRDPTLNCS_OPC_NCCFGRDNCS - NCCFGRDNCS_OPC_NCLTRDNCS_OPC_IORDNCS_OPC_MSGSNCS - MSGSNCS_OPC_CFGWRNCS_OPC_LTWRNCS_OPC_NCIOWRNCS_OPC_NCP2PSREQ_OPC_INVITOEREQ_OPC_RDINVRSPCNFLTRSP_DATARSP_DATA_OPC_DATA_MRSP_DATA_OPC_DATA_ERSP_DATA_OPC_DATA_SIRSP_DATA_OPC_DATA_M_CMPORSP4 - DATA_M_CMPORSP_DATA_OPC_DATA_E_CMPORSP_DATA_OPC_DATA_SI_CMPORSP_DATA_OPC_RSPFWDIWBRSP_DATA_OPC_RSPFWDSWBRSP_DATA_OPC_RSPIWBRSP_DATA_OPC_RSPSWBRSP_DATA_OPC_DEBUG_DATARSP_NODATARSP_NODATA_OPC_FWDSRSP_NODATA_OPC_MIRCMPURSP_NODATA_OPC_CNFLTRSP_NODATA_OPC_FWDCNFLTORSP_NODATA_OPC_CMPOSNP_OPC_FCURSNP_OPC_FCODESNP_OPC_FDATASNP_OPC_FDATAMIGSNP_OPC_FINVOWNSNP_OPC_FINVWB_OPC_WBMTOIWB_OPC_WBMTOSWB_OPC_WBMTOEWB_OPC_NONSNPWRWB_OPC_MTOIPTLWB_OPC_MTOEPTLWB_OPC_NONSNPWRTLWB_OPC_PUSHMTOIWB_OPC_FLUSHWB_OPC_EVCTCLNWB_OPC_NONSNPRDWB - NONSNPRDFILT_NONENo extra filterFILT_LOCALFILT_REMOTEFILT_DATAFILT_NON_DATAFILT_DUAL_SLOTFILT_SINGLE_SLOTFILT_ISOCHFILT_SLOT0Filter on slot0 packetsFILT_SLOT1Filter on slot1 packetsFILT_SLOT2Filter on slot2 packetsFILT_LLCRD_NON_ZEROFILT_IMPL_NULLFLOWQ_AD_VNA_BTW_2_THRESHFLOWQ_AD_VNA_LE2FLOWQ_AK_VNA_LE3FLOWQ_BL_VNA_BTW_0_THRESHFLOWQ_BL_VNA_EQ0GV_BLOCKAD_VNA_EQ0AD_VNA_EQ1AD_VNA_EQ2AK_VNA_EQ0AK_VNA_EQ1AK_VNA_EQ2AK_VNA_EQ3D2UIntel IcelakeX CHA39 uncoreicx_unc_cha39uncore_cha_39Intel IcelakeX CHA38 uncoreicx_unc_cha38uncore_cha_38Intel IcelakeX CHA37 uncoreicx_unc_cha37uncore_cha_37Intel IcelakeX CHA36 uncoreicx_unc_cha36uncore_cha_36Intel IcelakeX CHA35 uncoreicx_unc_cha35uncore_cha_35Intel IcelakeX CHA34 uncoreicx_unc_cha34uncore_cha_34Intel IcelakeX CHA33 uncoreicx_unc_cha33uncore_cha_33Intel IcelakeX CHA32 uncoreicx_unc_cha32uncore_cha_32Intel IcelakeX CHA31 uncoreicx_unc_cha31uncore_cha_31Intel IcelakeX CHA30 uncoreicx_unc_cha30uncore_cha_30Intel IcelakeX CHA29 uncoreicx_unc_cha29uncore_cha_29Intel IcelakeX CHA28 uncoreicx_unc_cha28uncore_cha_28Intel IcelakeX CHA27 uncoreicx_unc_cha27Intel IcelakeX CHA26 uncoreicx_unc_cha26Intel IcelakeX CHA25 uncoreicx_unc_cha25Intel IcelakeX CHA24 uncoreicx_unc_cha24Intel IcelakeX CHA23 uncoreicx_unc_cha23Intel IcelakeX CHA22 uncoreicx_unc_cha22Intel IcelakeX CHA21 uncoreicx_unc_cha21Intel IcelakeX CHA20 uncoreicx_unc_cha20Intel IcelakeX CHA19 uncoreicx_unc_cha19Intel IcelakeX CHA18 uncoreicx_unc_cha18Intel IcelakeX CHA17 uncoreicx_unc_cha17Intel IcelakeX CHA16 uncoreicx_unc_cha16Intel IcelakeX CHA15 uncoreicx_unc_cha15Intel IcelakeX CHA14 uncoreicx_unc_cha14Intel IcelakeX CHA13 uncoreicx_unc_cha13Intel IcelakeX CHA12 uncoreicx_unc_cha12Intel IcelakeX CHA11 uncoreicx_unc_cha11Intel IcelakeX CHA10 uncoreicx_unc_cha10Intel IcelakeX CHA9 uncoreicx_unc_cha9Intel IcelakeX CHA8 uncoreicx_unc_cha8Intel IcelakeX CHA7 uncoreicx_unc_cha7Intel IcelakeX CHA6 uncoreicx_unc_cha6Intel IcelakeX CHA5 uncoreicx_unc_cha5Intel IcelakeX CHA4 uncoreicx_unc_cha4Intel IcelakeX CHA3 uncoreicx_unc_cha3Intel IcelakeX CHA2 uncoreicx_unc_cha2Intel IcelakeX CHA1 uncoreicx_unc_cha1Intel IcelakeX CHA0 uncoreicx_unc_cha0UNC_CHA_2LM_NM_INVITOXUNC_CHA_2LM_NM_SETCONFLICTSUNC_CHA_2LM_NM_SETCONFLICTS2UNC_CHA_AG0_AD_CRD_ACQUIRED0UNC_CHA_AG0_AD_CRD_ACQUIRED1UNC_CHA_AG0_AD_CRD_OCCUPANCY0UNC_CHA_AG0_AD_CRD_OCCUPANCY1UNC_CHA_AG0_BL_CRD_ACQUIRED0UNC_CHA_AG0_BL_CRD_ACQUIRED1UNC_CHA_AG0_BL_CRD_OCCUPANCY0UNC_CHA_AG0_BL_CRD_OCCUPANCY1UNC_CHA_AG1_AD_CRD_ACQUIRED0UNC_CHA_AG1_AD_CRD_ACQUIRED1UNC_CHA_AG1_AD_CRD_OCCUPANCY0UNC_CHA_AG1_AD_CRD_OCCUPANCY1UNC_CHA_AG1_BL_CRD_ACQUIRED0UNC_CHA_AG1_BL_CRD_ACQUIRED1UNC_CHA_AG1_BL_CRD_OCCUPANCY0UNC_CHA_AG1_BL_CRD_OCCUPANCY1UNC_CHA_BYPASS_CHA_IMCCHA to iMC BypassUNC_CHA_CLOCKTICKSUNC_CHA_CMS_CLOCKTICKSCMS ClockticksUNC_CHA_CORE_SNPCore Cross Snoops IssuedUNC_CHA_COUNTER0_OCCUPANCYUNC_CHA_DIRECT_GODirect GOUNC_CHA_DIRECT_GO_OPCUNC_CHA_DIR_LOOKUPUNC_CHA_DIR_UPDATEUNC_CHA_DISTRESS_ASSERTEDDistress signal assertedUNC_CHA_EGRESS_ORDERINGUNC_CHA_HITME_HITUNC_CHA_HITME_LOOKUPUNC_CHA_HITME_MISSUNC_CHA_HITME_UPDATEUNC_CHA_HORZ_RING_AD_IN_USEHorizontal AD Ring In UseUNC_CHA_HORZ_RING_AKC_IN_USEHorizontal AK Ring In UseUNC_CHA_HORZ_RING_AK_IN_USEUNC_CHA_HORZ_RING_BL_IN_USEHorizontal BL Ring in UseUNC_CHA_HORZ_RING_IV_IN_USEHorizontal IV Ring in UseUNC_CHA_IMC_READS_COUNTUNC_CHA_IMC_WRITES_COUNTUNC_CHA_LLC_LOOKUPUNC_CHA_LLC_VICTIMSUNC_CHA_MISCUNC_CHA_MISC_EXTERNALUNC_CHA_OSBOSB Snoop BroadcastUNC_CHA_PMM_QOSUNC_CHA_PMM_QOS.SLOW_INSERTUNC_CHA_PMM_QOS_OCCUPANCYUNC_CHA_READ_NO_CREDITSUNC_CHA_REQUESTSUNC_CHA_RING_BOUNCES_HORZUNC_CHA_RING_BOUNCES_VERTUNC_CHA_RING_SRC_THRTLUNC_CHA_RxC_INSERTSUNC_CHA_RxC_IPQ0_REJECTUNC_CHA_RxC_IPQ1_REJECTUNC_CHA_RxC_IRQ0_REJECTUNC_CHA_RxC_IRQ1_REJECTUNC_CHA_RxC_ISMQ0_REJECTISMQ Rejects - Set 0UNC_CHA_RxC_ISMQ0_RETRYISMQ Retries - Set 0UNC_CHA_RxC_ISMQ1_REJECTISMQ Rejects - Set 1UNC_CHA_RxC_ISMQ1_RETRYISMQ Retries - Set 1UNC_CHA_RxC_OCCUPANCYIngress (from CMS) OccupancyUNC_CHA_RxC_OTHER0_RETRYOther Retries - Set 0UNC_CHA_RxC_OTHER1_RETRYOther Retries - Set 1UNC_CHA_RxC_PRQ0_REJECTUNC_CHA_RxC_PRQ1_REJECTUNC_CHA_RxC_REQ_Q0_RETRYRequest Queue Retries - Set 0UNC_CHA_RxC_REQ_Q1_RETRYRequest Queue Retries - Set 1UNC_CHA_RxC_RRQ0_REJECTRRQ Rejects - Set 0UNC_CHA_RxC_RRQ1_REJECTRRQ Rejects - Set 1UNC_CHA_RxC_WBQ0_REJECTWBQ Rejects - Set 0UNC_CHA_RxC_WBQ1_REJECTWBQ Rejects - Set 1UNC_CHA_RxR_BUSY_STARVEDUNC_CHA_RxR_BYPASSTransgress Ingress BypassUNC_CHA_RxR_CRD_STARVEDUNC_CHA_RxR_CRD_STARVED_1UNC_CHA_RxR_INSERTSUNC_CHA_RxR_OCCUPANCYTransgress Ingress OccupancyUNC_CHA_SF_EVICTIONUNC_CHA_SNOOPS_SENTSnoops SentUNC_CHA_SNOOP_RESPUNC_CHA_SNOOP_RESP_LOCALUNC_CHA_SNOOP_RSP_MISCMisc Snoop Responses ReceivedUNC_CHA_TOR_INSERTSUNC_CHA_TOR_OCCUPANCYUNC_CHA_TxR_HORZ_ADS_USEDCMS Horizontal ADS UsedUNC_CHA_TxR_HORZ_BYPASSCMS Horizontal Bypass UsedUNC_CHA_TxR_HORZ_CYCLES_FULLUNC_CHA_TxR_HORZ_CYCLES_NEUNC_CHA_TxR_HORZ_INSERTSCMS Horizontal Egress InsertsUNC_CHA_TxR_HORZ_NACKCMS Horizontal Egress NACKsUNC_CHA_TxR_HORZ_OCCUPANCYUNC_CHA_TxR_HORZ_STARVEDUNC_CHA_TxR_VERT_ADS_USEDCMS Vertical ADS UsedUNC_CHA_TxR_VERT_BYPASSUNC_CHA_TxR_VERT_BYPASS_1UNC_CHA_TxR_VERT_CYCLES_FULL0UNC_CHA_TxR_VERT_CYCLES_FULL1UNC_CHA_TxR_VERT_CYCLES_NE0UNC_CHA_TxR_VERT_CYCLES_NE1UNC_CHA_TxR_VERT_INSERTS0CMS Vert Egress AllocationsUNC_CHA_TxR_VERT_INSERTS1UNC_CHA_TxR_VERT_NACK0CMS Vertical Egress NACKsUNC_CHA_TxR_VERT_NACK1UNC_CHA_TxR_VERT_OCCUPANCY0CMS Vert Egress OccupancyUNC_CHA_TxR_VERT_OCCUPANCY1UNC_CHA_TxR_VERT_STARVED0UNC_CHA_TxR_VERT_STARVED1UNC_CHA_VERT_RING_AD_IN_USEVertical AD Ring In UseUNC_CHA_VERT_RING_AKC_IN_USEVertical AKC Ring In UseUNC_CHA_VERT_RING_AK_IN_USEVertical AK Ring In UseUNC_CHA_VERT_RING_BL_IN_USEVertical BL Ring in UseUNC_CHA_VERT_RING_IV_IN_USEVertical IV Ring in UseUNC_CHA_VERT_RING_TGC_IN_USEVertical TGC Ring In UseUNC_CHA_WB_PUSH_MTOIWbPushMtoIUNC_CHA_WRITE_NO_CREDITSUNC_CHA_XPT_PREFXPT PrefetchesDROP0_CONFLICTDROP0_NOCRDDROP1_CONFLICTDROP1_NOCRDSENT0Sent (on 0?) (experimental)SENT1Sent (on 1?) (experimental)MC0MC0 (experimental)MC1MC1 (experimental)MC10MC10 (experimental)MC11MC11 (experimental)MC12MC12 (experimental)MC13MC13 (experimental)MC2MC2 (experimental)MC3MC3 (experimental)MC4MC4 (experimental)MC5MC5 (experimental)MC6MC6 (experimental)MC7MC7 (experimental)MC8MC8 (experimental)MC9MC9 (experimental)Pushed to LLC (experimental)Down and Even (experimental)Down and Odd (experimental)Up and Even (experimental)Up and Odd (experimental)Down (experimental)Up (experimental)AKC_AG0AKC - Agent 0 (experimental)AKC_AG1AKC - Agent 1 (experimental)TGCAD - Agent 0 (experimental)AD - Agent 1 (experimental)AK - Agent 0 (experimental)AK - Agent 1 (experimental)BL - Agent 0 (experimental)BL - Agent 1 (experimental)IV_AG0IV (experimental)IV - Agent 0 (experimental)IV_AG1IV - Agent 1 (experimental)AD - All (experimental)AD_UNCRDAK (experimental)AKC_UNCRDBL_ALLBL - All (experimental)BL_UNCRDAD - Credited (experimental)BL - Credited (experimental)DDR4 Access (experimental)Just Hits (experimental)All requests from iA CoresIA_CLFLUSHIA_CLFLUSHOPTIA_CRDCRDs issued by iA CoresIA_CRD_PREFTBD (experimental)IA_DRDDRds issued by iA CoresIA_DRDPTEIA_DRD_OPTIA_DRD_OPT_PREFIA_DRD_PREFIA_HIT_CRDIA_HIT_CRD_PREFIA_HIT_DRDIA_HIT_DRDPTEIA_HIT_DRD_OPTIA_HIT_DRD_OPT_PREFIA_HIT_DRD_PREFIA_HIT_ITOMIA_HIT_LLCPREFCODEIA_HIT_LLCPREFDATAIA_HIT_LLCPREFRFOIA_HIT_RFOIA_HIT_RFO_PREFIA_ITOMIA_ITOMCACHENEARIA_LLCPREFCODEIA_LLCPREFDATAIA_LLCPREFRFOIA_MISS_CRDIA_MISS_CRD_LOCALIA_MISS_CRD_PREFIA_MISS_CRD_PREF_LOCALIA_MISS_CRD_PREF_REMOTEIA_MISS_CRD_REMOTEIA_MISS_DRDIA_MISS_DRDPTEIA_MISS_DRD_DDRIA_MISS_DRD_LOCALIA_MISS_DRD_LOCAL_DDRIA_MISS_DRD_LOCAL_PMMIA_MISS_DRD_OPTIA_MISS_DRD_OPT_PREFIA_MISS_DRD_PMMIA_MISS_DRD_PREFIA_MISS_DRD_PREF_DDRIA_MISS_DRD_PREF_LOCALIA_MISS_DRD_PREF_LOCAL_DDRIA_MISS_DRD_PREF_LOCAL_PMMIA_MISS_DRD_PREF_PMMIA_MISS_DRD_PREF_REMOTEIA_MISS_DRD_PREF_REMOTE_DDRIA_MISS_DRD_PREF_REMOTE_PMMIA_MISS_DRD_REMOTEIA_MISS_DRD_REMOTE_DDRIA_MISS_DRD_REMOTE_PMMIA_MISS_FULL_STREAMING_WRIA_MISS_FULL_STREAMING_WR_DDRIA_MISS_FULL_STREAMING_WR_PMMIA_MISS_ITOMIA_MISS_LLCPREFCODEIA_MISS_LLCPREFDATAIA_MISS_LLCPREFRFOIA_MISS_LOCAL_WCILF_DDRIA_MISS_LOCAL_WCILF_PMMIA_MISS_LOCAL_WCIL_DDRIA_MISS_LOCAL_WCIL_PMMIA_MISS_PARTIAL_STREAMING_WRIA_MISS_REMOTE_WCILF_DDRIA_MISS_REMOTE_WCILF_PMMIA_MISS_REMOTE_WCIL_DDRIA_MISS_REMOTE_WCIL_PMMIA_MISS_RFOIA_MISS_RFO_LOCALIA_MISS_RFO_PREFIA_MISS_RFO_PREF_LOCALIA_MISS_RFO_PREF_REMOTEIA_MISS_RFO_REMOTEIA_MISS_SPECITOMIA_MISS_UCRDFIA_MISS_WCILIA_MISS_WCILFIA_MISS_WCILF_DDRIA_MISS_WCILF_PMMIA_MISS_WCIL_DDRIA_MISS_WCIL_PMMIA_MISS_WILIA_RFORFOs issued by iA CoresIA_RFO_PREFIA_SPECITOMIA_WBMTOIIA_WCILIA_WCILFAll requests from IO DevicesIO_CLFLUSHIO_HIT_ITOMIO_HIT_ITOMCACHENEARIO_HIT_PCIRDCURIO_HIT_RFOIO_ITOMIO_ITOMCACHENEARIO_MISS_ITOMIO_MISS_ITOMCACHENEARIO_MISS_PCIRDCURIO_MISS_RFOIO_PCIRDCURIO_RFOIO_WBMTOIIPQ (experimental)IRQ_IAIRQ - iA (experimental)IRQ_NON_IAIRQ - Non iA (experimental)ISOCJust ISOC (experimental)LOCAL_TGTLOC_ALLLOC_IALOC_IOMATCH_OPCJust Misses (experimental)MMCFGMMCFG Access (experimental)Just NearMem (experimental)NONCOHNOT_NEARMEMPMM Access (experimental)PREMORPH_OPCPRQ - IOSF (experimental)PRQ_NON_IOSFPRQ - Non IOSF (experimental)REMOTE_TGTDDR4CLFlushes issued by iA CoresDRd_Prefs issued by iA CoresIA_HIT_LLCPREFCRDIA_HIT_LLCPREFDRDIA_HIT_SPECITOMLLCPrefRFO issued by iA CoresRFO_Prefs issued by iA CoresSpecItoMs issued by iA CoresIA_WBEFTOEIA_WBEFTOIIA_WBMTOEIA_WBSTOIItoMs issued by IO DevicesIO_ITOMCACHENEAR_LOCALIO_ITOMCACHENEAR_REMOTEIO_ITOM_LOCALIO_ITOM_REMOTEPRQ_IOSFRRQ (experimental)WBQ (experimental)TGR10TGR8TGR9TGR6MTOI_RSPDATAMMtoI RspIDataM (experimental)MTOI_RSPIFWDMMtoI RspIFwdM (experimental)PULLDATAPTL_HITLLCPULLDATAPTL_HITSFRSPIFWDMPTL_HITLLCRSPIFWDMPTL_HITSFRspCnflct (experimental)RspFwd (experimental)RSPFWDWBRsp*FWD*WB (experimental)RspI (experimental)RspIFwd (experimental)RspS (experimental)RspSFwd (experimental)RSPWBRsp*WB (experimental)RSPCNFLCT* (experimental)Rsp*Fwd*WB (experimental)IFV - Credited (experimental)Allow Snoop (experimental)ANY0 (experimental)HA (experimental)LLC OR SF Way (experimental)LLC Victim (experimental)PhyAddr Match (experimental)SF Victim (experimental)AD REQ on VN0 (experimental)AD RSP on VN0 (experimental)BL NCB on VN0 (experimental)BL NCS on VN0 (experimental)BL RSP on VN0 (experimental)BL WB on VN0 (experimental)IRQ (experimental)LLC or SF Way (experimental)IRQ Rejected (experimental)PRQ (experimental)DDR_FAST_FIFODDR_SLOW_FIFODDR4_FAST_INSERTREJ_IRQSLOWTORQ_SKIPTHROTTLE_IRQTHROTTLE_PRQIODCMEMWRMEMWRNISETCONFLICTLOCAL_INVITOELocal InvItoE (experimental)LOCAL_READLocal Rd (experimental)OFF_PWRHEURISTICOff (experimental)REMOTE_READRemote Rd (experimental)REMOTE_READINVITOERFO_HITS_SNP_BCASTMBE_INST0MBE_INST1All Lines VictimizedLOCAL_ONLYLocal Only (experimental)REMOTE_ONLYRemote Only (experimental)ALL_REMOTEANY_FCODE_LOCALCODE_READCode Reads (experimental)CODE_READ_FCODE_READ_LOCALCODE_READ_MISSCODE_READ_REMOTECODE_REMOTECOREPREF_OR_DMND_LOCAL_FDATA_READ_ALLDATA_READ_FDATA_READ_LOCALDATA_READ_REMOTEDMND_READ_LOCALE State (experimental)F State (experimental)FLUSH_INV_LOCALFLUSH_INV_REMOTEFLUSH_OR_INV_FI State (experimental)LLCPREF_LOCALLLCPREF_LOCAL_FLLC_PF_LOCALLOCALLY_HOMED_ADDRESSM State (experimental)All Misses (experimental)OTHER_REQ_FPREF_OR_DMND_REMOTE_FREAD_LOCAL_LOC_HOMREAD_LOCAL_REM_HOMRead Misses (experimental)READ_MISS_LOC_HOMREAD_MISS_REM_HOMREAD_REMOTE_LOC_HOMREAD_SF_HITREMOTELY_HOMED_ADDRESSREMOTE_SNOOP_FREMOTE_SNPRFO Requests (experimental)RFO_FRFO Misses (experimental)S State (experimental)WRITES_AND_OTHERWRITE_LOCALWRITE_REMOTEFull Line Non-ISOCHISOCH Partial (experimental)ISOCH (experimental)Left (experimental)Right (experimental)Left and Even (experimental)Left and Odd (experimental)Right and Even (experimental)Right and Odd (experimental)DPT_LOCALDPT Local (experimental)DPT_NONLOCALDPT Remote (experimental)DPT_STALL_IVDPT_STALL_NOCRDHorizontal (experimental)PMM_LOCALPMM Local (experimental)PMM_NONLOCALPMM Remote (experimental)Vertical (experimental)Snoop Needed (experimental)EXTCMPFAST_GOFAST_GO_PULLIDLE_DUE_SUPPRESSHA_SUPPRESS_DRDHA_SUPPRESS_NO_D2CHA_TOR_DEALLOCREMOTE_GTONEREMOTE_ONENot Taken (experimental)icx_unc_imc11uncore_imc_11icx_unc_imc10uncore_imc_10icx_unc_imc9uncore_imc_9icx_unc_imc8uncore_imc_8icx_unc_imc7icx_unc_imc6icx_unc_imc5icx_unc_imc4icx_unc_imc3icx_unc_imc2icx_unc_imc1icx_unc_imc0DRAM ClockticksUNC_M_CLOCKTICKS_FREERUNUNC_M_HCLOCKTICKSHalf clockticks for IMCUNC_M_PARITY_ERRORSUNC_M_PCLSUNC_M_PCLS.RDUNC_M_PMM_CMD1PMM CommandsUNC_M_PMM_CMD2PMM Commands - Part 2UNC_M_PMM_RPQ_CYCLES_FULLUNC_M_PMM_RPQ_CYCLES_NEUNC_M_PMM_RPQ_INSERTSPMM Read Queue InsertsUNC_M_PMM_RPQ_OCCUPANCYUNC_M_PMM_WPQ_CYCLES_FULLUNC_M_PMM_WPQ_CYCLES_NEUNC_M_PMM_WPQ_FLUSHUNC_M_PMM_WPQ_FLUSH_CYCUNC_M_PMM_WPQ_INSERTSPMM Write Queue InsertsUNC_M_PMM_WPQ_OCCUPANCYUNC_M_RDB_FULLUNC_M_RDB_INSERTSUNC_M_RDB_NOT_EMPTYUNC_M_RDB_OCCUPANCYUNC_M_RPQ_CYCLES_FULL_PCH0UNC_M_RPQ_CYCLES_FULL_PCH1UNC_M_RPQ_OCCUPANCY_PCH0UNC_M_RPQ_OCCUPANCY_PCH1UNC_M_SB_ACCESSESScoreboard AccessesUNC_M_SB_CANARYUNC_M_SB_CYCLES_FULLUNC_M_SB_CYCLES_NEUNC_M_SB_INSERTSScoreboard InsertsUNC_M_SB_OCCUPANCYScoreboard OccupancyUNC_M_SB_PREF_INSERTSScoreboard Prefetch InsertsUNC_M_SB_PREF_OCCUPANCYScoreboard Prefetch OccupancyUNC_M_SB_REJECTUNC_M_SB_STRV_ALLOCUNC_M_SB_STRV_DEALLOCUNC_M_SB_STRV_OCCUNC_M_SB_TAGGEDUNC_M_SB_TAGGED.NEWUNC_M_TAGCHK2LM Tag CheckUNC_M_WPQ_CYCLES_FULL_PCH0UNC_M_WPQ_CYCLES_FULL_PCH1UNC_M_WPQ_OCCUPANCY_PCH0UNC_M_WPQ_OCCUPANCY_PCH1MISS_CLEANMiss, no data in this lineMISS_DIRTYNM_RD_HITRead Hit in Near Memory CacheNM_WR_HITDDR4_CMPPMM0_CMPPMM1_CMPPMM2_CMPFMRDFMTGRFMWRFM_RDFar Mem Read (experimental)FM_TGRFM_WRFar Mem Write (experimental)NMRDNMWRNM_RDNear Mem Read (experimental)NM_WRNear Mem Write (experimental)DDR_EARLY_CMPFM_ADDR_CNFLTNM_SET_CNFLTPATROL_SET_CNFLTDDR4 (experimental)PMEMPersistent Mem (experimental)BLOCK_RDSBLOCK_WRSPMM_RDSPMM_WRSAlloc (experimental)Dealloc (experimental)FMRD_STARVEDFMTGRWR_STARVEDFMWR_STARVEDFM_RD_STARVEDFM_TGR_WR_STARVEDFM_WR_STARVEDNMRD_STARVEDNMWR_STARVEDNM_RD_STARVEDNM_WR_STARVEDReject (experimental)FMRD_CMPSFMWR_CMPSFM_RD_CMPSWrite Accepts (experimental)FM_WR_CMPSWrite Rejects (experimental)NMRD_CMPSNMWR_CMPSNM_RD_CMPSNM_WR_CMPSRead Accepts (experimental)Read Rejects (experimental)PGTPrecharge due to page tableLOW_0DIMM ID (experimental)LOW_1LOW_2LOW_3GNT_WAITNO_GNTNODATA_EXPNODATA_UNEXPOPP_RDPMM_ECC_ERRORECC Errors (experimental)PMM_ERID_ERRORPMM_ERID_STARVEDREQS_SLOT0REQS_SLOT1MISC_GNTMisc GNTs (experimental)Reads - RPQRPQ_GNTSRPQ GNTs (experimental)UFILL_RDUnderfill readsWPQ_GNTSUnderfill GNTs (experimental)OPPORTUNISTICRD_PRE_REGRD_PRE_UNDERFILLWR_NONPREWR_PREAll ActivatesIntel IcelakeX M2M1 uncoreicx_unc_m2m1Intel IcelakeX M2M0 uncoreicx_unc_m2m0UNC_M2M_AG0_AD_CRD_ACQUIRED0UNC_M2M_AG0_AD_CRD_ACQUIRED1UNC_M2M_AG0_AD_CRD_OCCUPANCY0UNC_M2M_AG0_AD_CRD_OCCUPANCY1UNC_M2M_AG0_BL_CRD_ACQUIRED0UNC_M2M_AG0_BL_CRD_ACQUIRED1UNC_M2M_AG0_BL_CRD_OCCUPANCY0UNC_M2M_AG0_BL_CRD_OCCUPANCY1UNC_M2M_AG1_AD_CRD_ACQUIRED0UNC_M2M_AG1_AD_CRD_ACQUIRED1UNC_M2M_AG1_AD_CRD_OCCUPANCY0UNC_M2M_AG1_AD_CRD_OCCUPANCY1UNC_M2M_AG1_BL_CRD_ACQUIRED0UNC_M2M_AG1_BL_CRD_ACQUIRED1UNC_M2M_AG1_BL_CRD_OCCUPANCY0UNC_M2M_AG1_BL_CRD_OCCUPANCY1UNC_M2M_BYPASS_M2M_EGRESSM2M to iMC BypassUNC_M2M_BYPASS_M2M_INGRESSUNC_M2M_CLOCKTICKSUNC_M2M_CMS_CLOCKTICKSUNC_M2M_DIRECTORY_HITDirectory HitUNC_M2M_DIRECTORY_LOOKUPUNC_M2M_DIRECTORY_MISSDirectory MissUNC_M2M_DIRECTORY_UPDATEUNC_M2M_DISTRESS_ASSERTEDUNC_M2M_DISTRESS_PMMUNC_M2M_DISTRESS_PMM_MEMMODEUNC_M2M_EGRESS_ORDERINGUNC_M2M_HORZ_RING_AD_IN_USEUNC_M2M_HORZ_RING_AKC_IN_USEUNC_M2M_HORZ_RING_AK_IN_USEUNC_M2M_HORZ_RING_BL_IN_USEUNC_M2M_HORZ_RING_IV_IN_USEUNC_M2M_IMC_READSM2M Reads Issued to iMCUNC_M2M_IMC_WRITESM2M Writes Issued to iMCUNC_M2M_MIRR_WRQ_INSERTSUNC_M2M_MIRR_WRQ_OCCUPANCYUNC_M2M_MISC_EXTERNALUNC_M2M_PKT_MATCHNumber Packet Header MatchesUNC_M2M_PREFCAM_CIS_DROPSUNC_M2M_PREFCAM_CYCLES_FULLPrefetch CAM Cycles FullUNC_M2M_PREFCAM_CYCLES_NEPrefetch CAM Cycles Not EmptyUNC_M2M_PREFCAM_DEALLOCSPrefetch CAM DeallocsUNC_M2M_PREFCAM_DEMAND_DROPSData Prefetches DroppedUNC_M2M_PREFCAM_DEMAND_MERGEUNC_M2M_PREFCAM_INSERTSPrefetch CAM InsertsUNC_M2M_PREFCAM_OCCUPANCYPrefetch CAM OccupancyUNC_M2M_PREFCAM_RESP_MISSUNC_M2M_PREFCAM_RxC_CYCLES_NEUNC_M2M_PREFCAM_RxC_DEALLOCSUNC_M2M_PREFCAM_RxC_INSERTSUNC_M2M_RING_BOUNCES_HORZUNC_M2M_RING_BOUNCES_VERTUNC_M2M_RING_SRC_THRTLUNC_M2M_RPQ_NO_REG_CRDUNC_M2M_RPQ_NO_REG_CRD_PMMUNC_M2M_RPQ_NO_SPEC_CRDUNC_M2M_RxC_AD_CYCLES_FULLUNC_M2M_RxC_AD_CYCLES_NEUNC_M2M_RxC_AD_INSERTSUNC_M2M_RxC_AD_OCCUPANCYUNC_M2M_RxC_AD_PREF_OCCUPANCYUNC_M2M_RxC_AK_WR_CMPUNC_M2M_RxC_BL_CYCLES_FULLUNC_M2M_RxC_BL_CYCLES_NEUNC_M2M_RxC_BL_INSERTSUNC_M2M_RxC_BL_OCCUPANCYUNC_M2M_RxR_BUSY_STARVEDUNC_M2M_RxR_BYPASSUNC_M2M_RxR_CRD_STARVEDUNC_M2M_RxR_CRD_STARVED_1UNC_M2M_RxR_INSERTSUNC_M2M_RxR_OCCUPANCYUNC_M2M_SCOREBOARD_RD_ACCEPTSUNC_M2M_SCOREBOARD_RD_REJECTSUNC_M2M_SCOREBOARD_WR_ACCEPTSUNC_M2M_SCOREBOARD_WR_REJECTSUNC_M2M_TAG_HITTag HitUNC_M2M_TAG_MISSTag Miss (experimental)UNC_M2M_TGR_AD_CREDITSUNC_M2M_TGR_BL_CREDITSUNC_M2M_TRACKER_FULLUNC_M2M_TRACKER_INSERTSUNC_M2M_TRACKER_NETracker Cycles Not EmptyUNC_M2M_TRACKER_OCCUPANCYUNC_M2M_TxC_AD_CYCLES_FULLUNC_M2M_TxC_AD_CYCLES_NEUNC_M2M_TxC_AD_INSERTSUNC_M2M_TxC_AD_OCCUPANCYUNC_M2M_TxC_AKUNC_M2M_TxC_AKC_CREDITSAKC Credits (experimental)UNC_M2M_TxC_AK_CYCLES_FULLAK Egress (to CMS) FullUNC_M2M_TxC_AK_CYCLES_NEAK Egress (to CMS) Not EmptyUNC_M2M_TxC_AK_INSERTSUNC_M2M_TxC_AK_OCCUPANCYAK Egress (to CMS) OccupancyUNC_M2M_TxC_BLUNC_M2M_TxC_BL_CYCLES_FULLBL Egress (to CMS) FullUNC_M2M_TxC_BL_CYCLES_NEBL Egress (to CMS) Not EmptyUNC_M2M_TxC_BL_INSERTSUNC_M2M_TxR_HORZ_ADS_USEDUNC_M2M_TxR_HORZ_BYPASSUNC_M2M_TxR_HORZ_CYCLES_FULLUNC_M2M_TxR_HORZ_CYCLES_NEUNC_M2M_TxR_HORZ_INSERTSUNC_M2M_TxR_HORZ_NACKUNC_M2M_TxR_HORZ_OCCUPANCYUNC_M2M_TxR_HORZ_STARVEDUNC_M2M_TxR_VERT_ADS_USEDUNC_M2M_TxR_VERT_BYPASSUNC_M2M_TxR_VERT_BYPASS_1UNC_M2M_TxR_VERT_CYCLES_FULL0UNC_M2M_TxR_VERT_CYCLES_FULL1UNC_M2M_TxR_VERT_CYCLES_NE0UNC_M2M_TxR_VERT_CYCLES_NE1UNC_M2M_TxR_VERT_INSERTS0UNC_M2M_TxR_VERT_INSERTS1UNC_M2M_TxR_VERT_NACK0UNC_M2M_TxR_VERT_NACK1UNC_M2M_TxR_VERT_OCCUPANCY0UNC_M2M_TxR_VERT_OCCUPANCY1UNC_M2M_TxR_VERT_STARVED0UNC_M2M_TxR_VERT_STARVED1UNC_M2M_VERT_RING_AD_IN_USEUNC_M2M_VERT_RING_AKC_IN_USEUNC_M2M_VERT_RING_AK_IN_USEUNC_M2M_VERT_RING_BL_IN_USEUNC_M2M_VERT_RING_IV_IN_USEUNC_M2M_VERT_RING_TGC_IN_USEUNC_M2M_WPQ_FLUSHWPQ FlushUNC_M2M_WPQ_NO_REG_CRDUNC_M2M_WPQ_NO_REG_CRD_PMMUNC_M2M_WPQ_NO_SPEC_CRDUNC_M2M_WR_TRACKER_FULLWrite Tracker Cycles FullUNC_M2M_WR_TRACKER_INSERTSWrite Tracker InsertsUNC_M2M_WR_TRACKER_NEUNC_M2M_WR_TRACKER_OCCUPANCYWrite Tracker OccupancyWrite Tracker Posted InsertsChannel 0 (experimental)Channel 1 (experimental)Channel 2 (experimental)MIRRMirror (experimental)MIRR_NONTGRMIRR_PWRData to Cache (experimental)Data to Core (experimental)Data to QPI (experimental)NM_RD_HIT_CLEANClean NearMem Read HitNM_RD_HIT_DIRTYDirty NearMem Read HitNM_UFILL_HIT_CLEANNM_UFILL_HIT_DIRTY1LM_POSTEDCISPMM_MEMMODE_ACCEPTSQUASHEDAll Channels (experimental)CH0_UPIUPI - Ch 0 (experimental)CH0_XPTXPT - Ch 0 (experimental)CH1_UPIUPI - Ch 1 (experimental)CH1_XPTXPT - Ch 1 (experimental)CH2_UPIUPI - Ch 2 (experimental)CH2_XPTXPT - Ch 2 (experimental)XPT_ALLCHERRORBLK_RxCNOT_PF_SAD_REGIONPF_AD_CRDPF_CAM_FULLPF_CAM_HITPF_SECURE_DROPRPQ_PROXYSTOP_B2BUPI_THRESHWPQ_PROXYXPT_THRESHCH0_XPTUPICH1_XPTUPICH2_XPTUPIXPTUPI_ALLCHCH0_HITA0_INVALCH0_HITA1_INVALCH0_MISS_INVALCH0_RSP_PDRESETCH1_HITA0_INVALCH1_HITA1_INVALCH1_MISS_INVALCH1_RSP_PDRESETCH2_HITA0_INVALCH2_HITA1_INVALCH2_MISS_INVALCH2_RSP_PDRESETMC Match (experimental)Mesh Match (experimental)CH0_ALLCH0_FROM_TGRFrom TGR - Ch0 (experimental)CH0_FULLCH0_FULL_ISOCHCH0_NICH0_NI_MISSCH0_PARTIALCH0_PARTIAL_ISOCHCH0_TO_DDR_AS_CACHECH0_TO_DDR_AS_MEMDDR - Ch0 (experimental)CH0_TO_PMMPMM - Ch0 (experimental)CH1_ALLCH1_FROM_TGRFrom TGR - Ch1 (experimental)CH1_FULLCH1_FULL_ISOCHCH1_NICH1_NI_MISSCH1_PARTIALCH1_PARTIAL_ISOCHCH1_TO_DDR_AS_CACHECH1_TO_DDR_AS_MEMDDR - Ch1 (experimental)CH1_TO_PMMPMM - Ch1 (experimental)PMM - All ChannelsCH0_ISOCHCH0_NORMALCH1_ISOCHCH1_NORMALCH2_FROM_TGRFrom TGR - Ch2 (experimental)Found in any stateFound in A stateFound in I stateFound in S stateIntel IcelakeX IIO5 uncoreicx_unc_iio5Intel IcelakeX IIO4 uncoreicx_unc_iio4Intel IcelakeX IIO3 uncoreicx_unc_iio3Intel IcelakeX IIO2 uncoreicx_unc_iio2Intel IcelakeX IIO1 uncoreicx_unc_iio1Intel IcelakeX IIO0 uncoreicx_unc_iio0UNC_IIO_BANDWIDTH_INUNC_IIO_BANDWIDTH_OUTUNC_IIO_CLOCKTICKSUNC_IIO_CLOCKTICKS_FREERUNUNC_IIO_COMP_BUF_OCCUPANCYUNC_IIO_DATA_REQ_BY_CPUData requested by the CPUUNC_IIO_DATA_REQ_OF_CPUUNC_IIO_INBOUND_ARB_REQIncoming arbitration requestsUNC_IIO_INBOUND_ARB_WONUNC_IIO_IOMMU0UNC_IIO_IOMMU1UNC_IIO_IOMMU3UNC_IIO_MASK_MATCH_ANDAND Mask/match for debug busUNC_IIO_MASK_MATCH_OROR Mask/match for debug busUNC_IIO_NOTHINGUNC_IIO_NUM_REQ_FROM_CPUUNC_IIO_NUM_REQ_OF_CPUUNC_IIO_NUM_REQ_OF_CPU_BY_TGTUNC_IIO_PWT_OCCUPANCYPWT occupancy (experimental)UNC_IIO_REQ_FROM_PCIE_CL_CMPLUNC_IIO_REQ_FROM_PCIE_CMPLPCIe Request completePCIe Request - pass completeUNC_IIO_SYMBOL_TIMESUNC_IIO_TXN_REQ_BY_CPUUNC_IIO_TXN_REQ_OF_CPUATOMIC_IOMMU0ATOMIC_IOMMU1ATOMIC_PART4ATOMIC_PART5ATOMIC_PART6ATOMIC_PART7CMPD_IOMMU0CMPD_IOMMU1CMPD_PART0CMPD_PART1CMPD_PART2CMPD_PART3CMPD_PART4CMPD_PART5CMPD_PART6CMPD_PART7MEM_READ_IOMMU0MEM_READ_IOMMU1Card reading from DRAMMEM_READ_PART4MEM_READ_PART5MEM_READ_PART6MEM_READ_PART7MEM_WRITE_IOMMU0MEM_WRITE_IOMMU1Card writing to DRAMMEM_WRITE_PART4MEM_WRITE_PART5MEM_WRITE_PART6MEM_WRITE_PART7MSG_IOMMU0MSG_IOMMU1MSG_PART4MSG_PART5MSG_PART6MSG_PART7PEER_READ_IOMMU0PEER_READ_IOMMU1PEER_READ_PART4PEER_READ_PART5PEER_READ_PART6PEER_READ_PART7PEER_WRITE_IOMMU0PEER_WRITE_IOMMU1PEER_WRITE_PART4PEER_WRITE_PART5PEER_WRITE_PART6PEER_WRITE_PART7CFG_READ_IOMMU0CFG_READ_IOMMU1CFG_READ_PART4CFG_READ_PART5CFG_READ_PART6CFG_READ_PART7CFG_WRITE_IOMMU0CFG_WRITE_IOMMU1CFG_WRITE_PART4CFG_WRITE_PART5CFG_WRITE_PART6CFG_WRITE_PART7IO_READ_IOMMU0IO_READ_IOMMU1IO_READ_PART4IO_READ_PART5IO_READ_PART6IO_READ_PART7IO_WRITE_IOMMU0IO_WRITE_IOMMU1IO_WRITE_PART4IO_WRITE_PART5IO_WRITE_PART6IO_WRITE_PART7FINAL_RD_WRREQ_OWNWriting line (experimental)IOMMU_HITIOMMU_REQTO_IOTo device (experimental)ABORTAbort (experimental)CONFINED_P2PConfined P2P (experimental)LOC_P2PLocal P2P (experimental)MCASTMulti-cast (experimental)MsgB (experimental)REM_P2PRemote P2P (experimental)UBOXUbox (experimental)ALL_DROPDrop request (experimental)COMMIT_ALLIRPFrom IRP (experimental)From ITC (experimental)PREALLOCNon-PCIE bus (experimental)INT_CACHE_HITSINT_CACHE_LOOKUPSNUM_CTXT_CACHE_INVAL_DEVICENUM_CTXT_CACHE_INVAL_DOMAINNUM_CTXT_CACHE_INVAL_GBLNUM_INVAL_DOMAINNUM_INVAL_GBLNUM_INVAL_PAGECYC_PWT_FULLNUM_MEM_ACCESSESPWC_1G_HITSPWC_2M_HITSPWC_4K_HITSPWC_512G_HITSPWC_CACHE_FILLSPWT_CACHE_LOOKUPSALL_LOOKUPSCTXT_CACHE_HITSCTXT_CACHE_LOOKUPSFIRST_LOOKUPSCMPD_ALLPart 0-7 (experimental)CMPD_ALL_PARTSPart 0-7Part 0Part 1Part 3Part 4Part 5Part 6Part 7PART0_FREERUNPART1_FREERUNPART2_FREERUNPART3_FREERUNPART4_FREERUNPART5_FREERUNPART6_FREERUNPART7_FREERUNIntel IcelakeX IRP5 uncoreicx_unc_irp5uncore_irp_5Intel IcelakeX IRP4 uncoreicx_unc_irp4uncore_irp_4Intel IcelakeX IRP3 uncoreicx_unc_irp3uncore_irp_3Intel IcelakeX IRP2 uncoreicx_unc_irp2uncore_irp_2Intel IcelakeX IRP1 uncoreicx_unc_irp1uncore_irp_1Intel IcelakeX IRP0 uncoreicx_unc_irp0uncore_irp_0FAF RF fullFAF allocation -- sent to ADQCounts Timeouts - Set 0Misc Events - Set 1P2P Requests (experimental)P2P Occupancy (experimental)P2P TransactionsUNC_I_TxC_AK_INSERTSUNC_I_TxC_BL_DRS_CYCLES_FULLUNC_I_TxC_BL_DRS_INSERTSUNC_I_TxC_BL_DRS_OCCUPANCYUNC_I_TxC_BL_NCB_CYCLES_FULLUNC_I_TxC_BL_NCB_INSERTSUNC_I_TxC_BL_NCB_OCCUPANCYUNC_I_TxC_BL_NCS_CYCLES_FULLUNC_I_TxC_BL_NCS_INSERTSUNC_I_TxC_BL_NCS_OCCUPANCYUNC_I_TxS_DATA_INSERTS_NCBUNC_I_TxS_DATA_INSERTS_NCSUNC_I_TxS_REQUEST_OCCUPANCYAtomic (experimental)Select Source (experimental)Other (experimental)ALL_HIT_ESALL_HIT_IALL_HIT_MHit E or S (experimental)Hit I (experimental)Hit M (experimental)SnpCode (experimental)SnpData (experimental)SnpInv (experimental)P2P Message (experimental)P2P reads (experimental)P2P Writes (experimental)Lost ForwardReceived Valid (experimental)SLOWPATH_FWPF_NO_PRFCLFlush (experimental)Any Source (experimental)Snoops (experimental)Intel IcelakeX PCU uncoreicx_unc_pcuUNC_P_FREQ_CLIP_AVX256UNC_P_FREQ_CLIP_AVX512Number of cores in C-StateVR Hot (experimental)C0 and C1 (experimental)C6 and C7 (experimental)Intel IcelakeX UPI3 uncoreicx_unc_upi3uncore_upi_3Intel IcelakeX UPI2 uncoreicx_unc_upi2Intel IcelakeX UPI1 uncoreicx_unc_upi1Intel IcelakeX UPI0 uncoreicx_unc_upi0Number of kfclksDirect packet attemptsL1 Req Nack (experimental)UNC_UPI_REQ_SLOT2_FROM_M3.VNAUNC_UPI_RxL0P_POWER_CYCLESCycles in L0p (experimental)UNC_UPI_RxL0_POWER_CYCLESCycles in L0 (experimental)UNC_UPI_RxL_BASIC_HDR_MATCHUNC_UPI_RxL_BYPASSEDRxQ Flit Buffer BypassedUNC_UPI_RxL_CRC_ERRORSUNC_UPI_RxL_FLITSValid Flits ReceivedUNC_UPI_RxL_INSERTSRxQ Flit Buffer AllocationsUNC_UPI_RxL_OCCUPANCYUNC_UPI_RxL_SLOT_BYPASSUNC_UPI_TxL0P_CLK_ACTIVEUNC_UPI_TxL0P_POWER_CYCLESUNC_UPI_TxL0_POWER_CYCLESUNC_UPI_TxL_BASIC_HDR_MATCHUNC_UPI_TxL_BYPASSEDUNC_UPI_TxL_FLITSValid Flits SentUNC_UPI_TxL_INSERTSUNC_UPI_TxL_OCCUPANCYIdle (experimental)All Non DataNCB_OPCNCS_OPCREQ_OPCRSP_DATA_OPCRSP_NODATA_OPCSNP_OPCWriteback (experimental)WB_OPCD2C (experimental)D2K (experimental)Intel IcelakeX M3UPI3 uncoreicx_unc_m3upi3uncore_m3upi_3Intel IcelakeX M3UPI2 uncoreicx_unc_m3upi2Intel IcelakeX M3UPI1 uncoreicx_unc_m3upi1Intel IcelakeX M3UPI0 uncoreicx_unc_m3upi0UNC_M3UPI_CLOCKTICKSUNC_M3UPI_CMS_CLOCKTICKSCMS Clockticks (experimental)UNC_M3UPI_D2C_SENTD2C Sent (experimental)UNC_M3UPI_D2U_SENTD2U Sent (experimental)UNC_M3UPI_DISTRESS_ASSERTEDUNC_M3UPI_EGRESS_ORDERINGUNC_M3UPI_HORZ_RING_AD_IN_USEUNC_M3UPI_HORZ_RING_AK_IN_USEUNC_M3UPI_HORZ_RING_BL_IN_USEUNC_M3UPI_HORZ_RING_IV_IN_USEUNC_M3UPI_M2_BL_CREDITS_EMPTYM2 BL Credits EmptyUNC_M3UPI_MISC_EXTERNALUNC_M3UPI_MULTI_SLOT_RCVDMulti Slot Flit ReceivedUNC_M3UPI_RING_BOUNCES_HORZUNC_M3UPI_RING_BOUNCES_VERTUNC_M3UPI_RING_SRC_THRTLUNC_M3UPI_RxC_ARB_LOST_VN0Lost Arb for VN0UNC_M3UPI_RxC_ARB_LOST_VN1Lost Arb for VN1UNC_M3UPI_RxC_ARB_MISCArb MiscellaneousUNC_M3UPI_RxC_ARB_NOCRD_VN0No Credits to Arb for VN0UNC_M3UPI_RxC_ARB_NOCRD_VN1No Credits to Arb for VN1UNC_M3UPI_RxC_ARB_NOREQ_VN0Can't Arb for VN0UNC_M3UPI_RxC_ARB_NOREQ_VN1Can't Arb for VN1UNC_M3UPI_RxC_BYPASSEDIngress Queue BypassesUNC_M3UPI_RxC_CRD_MISCMiscellaneous Credit EventsUNC_M3UPI_RxC_CRD_OCCUNC_M3UPI_RxC_CYCLES_NE_VN0UNC_M3UPI_RxC_CYCLES_NE_VN1Data Flit Not SentUNC_M3UPI_RxC_FLITS_GEN_BLUNC_M3UPI_RxC_FLITS_MISCUNC_M3UPI_RxC_FLITS_SLOT_BLUNC_M3UPI_RxC_FLIT_GEN_HDR1Flit Gen - Header 1UNC_M3UPI_RxC_FLIT_GEN_HDR2Flit Gen - Header 2UNC_M3UPI_RxC_HDR_FLITS_SENTSent Header FlitHeader Not SentUNC_M3UPI_RxC_HELDMessage HeldUNC_M3UPI_RxC_INSERTS_VN0UNC_M3UPI_RxC_INSERTS_VN1UNC_M3UPI_RxC_OCCUPANCY_VN0UNC_M3UPI_RxC_OCCUPANCY_VN1UNC_M3UPI_RxC_VNA_CRDRemote VNA CreditsUNC_M3UPI_RxC_VNA_CRD_MISCUNC_M3UPI_RxR_BUSY_STARVEDUNC_M3UPI_RxR_BYPASSUNC_M3UPI_RxR_CRD_STARVEDUNC_M3UPI_RxR_CRD_STARVED_1UNC_M3UPI_RxR_INSERTSUNC_M3UPI_RxR_OCCUPANCYUNC_M3UPI_TxC_AD_ARB_FAILFailed ARB for ADUNC_M3UPI_TxC_AD_FLQ_BYPASSAD FlowQ BypassAD Flow Q Not EmptyUNC_M3UPI_TxC_AD_FLQ_INSERTSAD Flow Q InsertsAD Flow Q OccupancyUNC_M3UPI_TxC_AK_FLQ_INSERTSUNC_M3UPI_TxC_BL_ARB_FAILFailed ARB for BLBL Flow Q Not EmptyUNC_M3UPI_TxC_BL_FLQ_INSERTSBL Flow Q InsertsBL Flow Q OccupancyUNC_M3UPI_TxR_HORZ_ADS_USEDUNC_M3UPI_TxR_HORZ_BYPASSUNC_M3UPI_TxR_HORZ_CYCLES_NEUNC_M3UPI_TxR_HORZ_INSERTSUNC_M3UPI_TxR_HORZ_NACKUNC_M3UPI_TxR_HORZ_OCCUPANCYUNC_M3UPI_TxR_HORZ_STARVEDUNC_M3UPI_TxR_VERT_ADS_USEDUNC_M3UPI_TxR_VERT_BYPASSUNC_M3UPI_TxR_VERT_BYPASS_1UNC_M3UPI_TxR_VERT_CYCLES_NE0UNC_M3UPI_TxR_VERT_CYCLES_NE1UNC_M3UPI_TxR_VERT_INSERTS0UNC_M3UPI_TxR_VERT_INSERTS1UNC_M3UPI_TxR_VERT_NACK0UNC_M3UPI_TxR_VERT_NACK1UNC_M3UPI_TxR_VERT_OCCUPANCY0UNC_M3UPI_TxR_VERT_OCCUPANCY1UNC_M3UPI_TxR_VERT_STARVED0UNC_M3UPI_TxR_VERT_STARVED1UPI0 AD Credits EmptyUPI0 BL Credits EmptyUNC_M3UPI_UPI_PREFETCH_SPAWNUNC_M3UPI_VERT_RING_AD_IN_USEUNC_M3UPI_VERT_RING_AK_IN_USEUNC_M3UPI_VERT_RING_BL_IN_USEUNC_M3UPI_VERT_RING_IV_IN_USEUNC_M3UPI_VN0_CREDITS_USEDUNC_M3UPI_VN0_NO_CREDITSVN0 No CreditsUNC_M3UPI_VN1_CREDITS_USEDVN1 Credit UsedUNC_M3UPI_VN1_NO_CREDITSVN1 No CreditsUNC_M3UPI_WB_OCC_COMPAREUNC_M3UPI_WB_PENDINGUNC_M3UPI_XPT_PFTCHUNC_M3UPI_XPT_PFTCH.ARRIVEDFLITTEDLOST_ARBLOST_OLDLOST_QFULLLOCAL_AND_RT_VN0LOCAL_AND_RT_VN1ROUTETHRU_VN0ROUTETHRU_VN1WAITING4PULL_VN0WAITING4PULL_VN1RT_EQ_LOCALDEST_VN0RT_EQ_LOCALDEST_VN1RT_GT_LOCALDEST_VN0RT_GT_LOCALDEST_VN1RT_LT_LOCALDEST_VN0RT_LT_LOCALDEST_VN1WB on BL (experimental)NCB on BL (experimental)REQ on AD (experimental)RSP on AD (experimental)SNP on AD (experimental)RSP on BL (experimental)VNA (experimental)VN0_LOCALVN0_THROUGHVN0_WRPULLVN1_LOCALVN1_THROUGHVN1_WRPULLREQ_ADBL_ALLOC_L5REQ_VN01_ALLOC_LT10VN0_JUST_ADVN0_JUST_BLVN0_ONLYVN1_JUST_ADVN1_JUST_BLVN1_ONLYAny In Use (experimental)Corrected (experimental)Level < 1 (experimental)Level < 10 (experimental)Level < 4 (experimental)Level < 5 (experimental)NCS on BL (experimental)Can't Slot AD (experimental)Can't Slot BL (experimental)VN1 (experimental)No BGF Credits (experimental)No TxQ Credits (experimental)TSV_HITSV High (experimental)VALID_FOR_FLITOne Message (experimental)Two Messages (experimental)Three Messages (experimental)One Slot Taken (experimental)Parallel Ok (experimental)Accumulate (experimental)AHEAD_MSG1_AFTERAHEAD_MSG1_DURINGAHEAD_MSG2_AFTERAHEAD_MSG2_SENTWait on Pump 0 (experimental)Wait on Pump 1 (experimental)S2REQ_IN_HOLDOFFS2REQ_IN_SERVICES2REQ_RECEIVEDS2REQ_WITHDRAWND2K Credits (experimental)VNA In Use (experimental)LT1_FOR_D2KLT2_FOR_D2KVN0_NO_D2K_FOR_ARBNo D2K For Arb (experimental)VN1_NO_D2K_FOR_ARBADBL_PARALLEL_WIN_VN0ADBL_PARALLEL_WIN_VN1ALL_PARALLEL_WINVN01_PARALLEL_WINAD - Slot 0 (experimental)AD - Slot 1 (experimental)AD - Slot 2 (experimental)AK - Slot 0 (experimental)AK - Slot 2 (experimental)BL - Slot 0 (experimental)IIO2 (experimental)IIO3 (experimental)IIO4 (experimental)IIO5 (experimental)UBOX_NCBVNA Messages (experimental)Writebacks (experimental)Intel IcelakeX UBOX uncoreicx_unc_uboxUNC_U_CLOCKTICKSMessage ReceivedUNC_U_M2U_MISC1UNC_U_M2U_MISC2UNC_U_M2U_MISC3Cycles PHOLD Assert to AckRACU Request (experimental)Assert to ACK (experimental)TxC_CYCLES_FULL_AKTxC_CYCLES_FULL_AKCRxC_CYCLES_EMPTY_BLRxC_CYCLES_FULL_BLTxC_CYCLES_CRD_OVF_VN0_NCBTxC_CYCLES_CRD_OVF_VN0_NCSTxC_CYCLES_EMPTY_AKTxC_CYCLES_EMPTY_AKCTxC_CYCLES_EMPTY_BLTxC_CYCLES_FULL_BLRxC_CYCLES_NE_CBO_NCBRxC_CYCLES_NE_CBO_NCSRxC_CYCLES_NE_UPI_NCBRxC_CYCLES_NE_UPI_NCSTxC_CYCLES_CRD_OVF_CBO_NCBTxC_CYCLES_CRD_OVF_CBO_NCSTxC_CYCLES_CRD_OVF_UPI_NCBTxC_CYCLES_CRD_OVF_UPI_NCSDoorbell (experimental)Interrupt (experimental)IPI (experimental)MSI (experimental)VLW (experimental)Intel IcelakeX M2PCIE2 uncoreicx_unc_m2pcie2uncore_m2pcie_2Intel IcelakeX M2PCIE1 uncoreicx_unc_m2pcie1uncore_m2pcie_1Intel IcelakeX M2PCIE0 uncoreicx_unc_m2pcie0uncore_m2pcie_0UNC_M2P_AG0_AD_CRD_ACQUIRED0UNC_M2P_AG0_AD_CRD_ACQUIRED1UNC_M2P_AG0_AD_CRD_OCCUPANCY0UNC_M2P_AG0_AD_CRD_OCCUPANCY1UNC_M2P_AG0_BL_CRD_ACQUIRED0UNC_M2P_AG0_BL_CRD_ACQUIRED1UNC_M2P_AG0_BL_CRD_OCCUPANCY0UNC_M2P_AG0_BL_CRD_OCCUPANCY1UNC_M2P_AG1_AD_CRD_ACQUIRED0UNC_M2P_AG1_AD_CRD_ACQUIRED1UNC_M2P_AG1_AD_CRD_OCCUPANCY0UNC_M2P_AG1_AD_CRD_OCCUPANCY1UNC_M2P_AG1_BL_CRD_ACQUIRED0UNC_M2P_AG1_BL_CRD_ACQUIRED1UNC_M2P_AG1_BL_CRD_OCCUPANCY0UNC_M2P_AG1_BL_CRD_OCCUPANCY1UNC_M2P_CLOCKTICKSUNC_M2P_CMS_CLOCKTICKSUNC_M2P_DISTRESS_ASSERTEDUNC_M2P_EGRESS_ORDERINGUNC_M2P_HORZ_RING_AD_IN_USEUNC_M2P_HORZ_RING_AKC_IN_USEUNC_M2P_HORZ_RING_AK_IN_USEUNC_M2P_HORZ_RING_BL_IN_USEUNC_M2P_HORZ_RING_IV_IN_USEUNC_M2P_IIO_CREDITS_ACQUIREDM2PCIe IIO Credit AcquiredUNC_M2P_IIO_CREDITS_REJECTUNC_M2P_IIO_CREDITS_USEDM2PCIe IIO Credits in UseUNC_M2P_MISC_EXTERNALUNC_M2P_P2P_CRD_OCCUPANCYP2P Credit OccupancyUNC_M2P_P2P_DED_RECEIVEDDedicated Credits ReceivedUNC_M2P_P2P_SHAR_RECEIVEDShared Credits  ReceivedUNC_M2P_RING_BOUNCES_HORZUNC_M2P_RING_BOUNCES_VERTUNC_M2P_RING_SRC_THRTLUNC_M2P_RxC_CYCLES_NEUNC_M2P_RxC_INSERTSUNC_M2P_RxR_BUSY_STARVEDUNC_M2P_RxR_BYPASSUNC_M2P_RxR_CRD_STARVEDUNC_M2P_RxR_CRD_STARVED_1UNC_M2P_RxR_INSERTSUNC_M2P_RxR_OCCUPANCYUNC_M2P_TxC_CREDITSUNC_M2P_TxC_CREDITS.PRQUNC_M2P_TxC_CYCLES_FULLEgress (to CMS) Cycles FullUNC_M2P_TxC_CYCLES_NEUNC_M2P_TxC_INSERTSEgress (to CMS) IngressUNC_M2P_TxR_HORZ_ADS_USEDUNC_M2P_TxR_HORZ_BYPASSUNC_M2P_TxR_HORZ_CYCLES_FULLUNC_M2P_TxR_HORZ_CYCLES_NEUNC_M2P_TxR_HORZ_INSERTSUNC_M2P_TxR_HORZ_NACKUNC_M2P_TxR_HORZ_OCCUPANCYUNC_M2P_TxR_HORZ_STARVEDUNC_M2P_TxR_VERT_ADS_USEDUNC_M2P_TxR_VERT_BYPASSUNC_M2P_TxR_VERT_BYPASS_1UNC_M2P_TxR_VERT_CYCLES_FULL0UNC_M2P_TxR_VERT_CYCLES_FULL1UNC_M2P_TxR_VERT_CYCLES_NE0UNC_M2P_TxR_VERT_CYCLES_NE1UNC_M2P_TxR_VERT_INSERTS0UNC_M2P_TxR_VERT_INSERTS1UNC_M2P_TxR_VERT_NACK0UNC_M2P_TxR_VERT_NACK1UNC_M2P_TxR_VERT_OCCUPANCY0UNC_M2P_TxR_VERT_OCCUPANCY1UNC_M2P_TxR_VERT_STARVED0UNC_M2P_TxR_VERT_STARVED1UNC_M2P_VERT_RING_AD_IN_USEUNC_M2P_VERT_RING_AKC_IN_USEUNC_M2P_VERT_RING_AK_IN_USEUNC_M2P_VERT_RING_BL_IN_USEUNC_M2P_VERT_RING_IV_IN_USEUNC_M2P_VERT_RING_TGC_IN_USEAD_0AD_1AK_CRD_0AK_CRD_1BL_0BL_1AK_0AK_1PMM_DISTRESS_0PMM_DISTRESS_1PMM_BLOCK_0PMM_BLOCK_1CHA_IDICHA_NCBCHA_NCSIIO_NCBIIO_NCSUPI2_DRSUPI2 - DRS (experimental)UPI2_NCBUPI2 - NCB (experimental)UPI2_NCSUPI2 - NCS (experimental)UPI0_DRSUPI0 - DRS (experimental)UPI0_NCBUPI0 - NCB (experimental)UPI0_NCSUPI0 - NCS (experimental)UPI1_DRSUPI1 - DRS (experimental)UPI1_NCBUPI1 - NCB (experimental)UPI1_NCSUPI1 - NCS (experimental)AGENT_0Agent0 (experimental)AGENT_1Agent1 (experimental)AGENT_2Agent2 (experimental)LOCAL_NCBLocal NCB (experimental)LOCAL_NCSLocal NCS (experimental)REMOTE_NCBRemote NCB (experimental)REMOTE_NCSRemote NCS (experimental)M2IOSF4_NCBM2IOSF4 - NCB (experimental)M2IOSF4_NCSM2IOSF4 - NCS (experimental)M2IOSF5_NCBM2IOSF5 - NCB (experimental)M2IOSF5_NCSM2IOSF5 - NCS (experimental)M2IOSF0_NCBM2IOSF0 - NCB (experimental)M2IOSF0_NCSM2IOSF0 - NCS (experimental)M2IOSF1_NCBM2IOSF1 - NCB (experimental)M2IOSF1_NCSM2IOSF1 - NCS (experimental)M2IOSF2_NCBM2IOSF2 - NCB (experimental)M2IOSF2_NCSM2IOSF2 - NCS (experimental)M2IOSF3_NCBM2IOSF3 - NCB (experimental)M2IOSF3_NCSM2IOSF3 - NCS (experimental)AGENT_3Agent3 (experimental)AGENT_4Agent4 (experimental)AGENT_5Agent5 (experimental)MS2IOSF4_NCBMS2IOSF4_NCSMS2IOSF5_NCBMS2IOSF5_NCSMS2IOSF0_NCBMS2IOSF0_NCSMS2IOSF1_NCBMS2IOSF1_NCSMS2IOSF2_NCBMS2IOSF2_NCSMS2IOSF3_NCBMS2IOSF3_NCSDRS_0DRS_1NCB_0NCB_1NCS_0NCS_1spr_unc_imc11spr_unc_imc10spr_unc_imc9spr_unc_imc8spr_unc_imc7spr_unc_imc6spr_unc_imc5spr_unc_imc4spr_unc_imc3spr_unc_imc2spr_unc_imc1spr_unc_imc0Count ActivationUNC_M_CAS_ISSUED_REQ_LENCycles in CKE modeThrottled CyclesRead Data Buffer InsertsUNC_M_RDB_NEScoreboard accesses2LM Tag checkRDB_1_ELEMRead buffer has 1 element(s)RDB_2_ELEMRead buffer has 2 element(s)RDB_3_ELEMRead buffer has 3 element(s)RDB_4_ELEMRead buffer has 4 element(s)RDB_5_ELEMRead buffer has 5 element(s)RDB_6_ELEMRead buffer has 6 element(s)RDB_7_ELEMRead buffer has 7 element(s)RDB_8_ELEMRead buffer has 8 element(s)RDB_9_ELEMRead buffer has 9 element(s)RDB_10_ELEMRead buffer has 10 element(s)RDB_11_ELEMRead buffer has 11 element(s)RDB_12_ELEMRead buffer has 12 element(s)RDB_13_ELEMRead buffer has 13 element(s)RDB_14_ELEMRead buffer has 14 element(s)RDB_15_ELEMRead buffer has 15 element(s)RDB_16_ELEMRead buffer has 16 element(s)RDB_17_ELEMRead buffer has 17 element(s)RDB_18_ELEMRead buffer has 18 element(s)RDB_19_ELEMRead buffer has 19 element(s)RDB_20_ELEMRead buffer has 20 element(s)RDB_21_ELEMRead buffer has 21 element(s)RDB_22_ELEMRead buffer has 22 element(s)RDB_23_ELEMRead buffer has 23 element(s)RDB_24_ELEMRead buffer has 24 element(s)Pseudo-channel 0Pseudo-channel 1PMM (experimental)DRAM Precharge commandsPGT_PCH0PGT_PCH1RD_PCH0RD_PCH1UFILLUFILL_PCH0UFILL_PCH1WR_PCH0WR_PCH1ALL_SCH0ALL_SCH1GNT_WAIT_SCH0GNT_WAIT_SCH1NO_GNT_SCH0NO_GNT_SCH1RD_32BRD_64BRD_UFILL_32BRD_UFILL_64BWR_32BWR_64BAll DRAM CAS commands issuedspr_unc_upi3spr_unc_upi2spr_unc_upi1spr_unc_upi0UPI ClockticksPHY Cycles (experimental)UNC_UPI_RxL_ANY_FLITSRxQ OccupancyUNC_UPI_TxL_ANY_FLITSFlits transmittedALL_LLCRDALL_LLCTRLAll LLCTRL (experimental)All Null FlitsALL_PROTHDRspr_unc_cha59uncore_cha_59spr_unc_cha58uncore_cha_58spr_unc_cha57uncore_cha_57spr_unc_cha56uncore_cha_56spr_unc_cha55uncore_cha_55spr_unc_cha54uncore_cha_54spr_unc_cha53uncore_cha_53spr_unc_cha52uncore_cha_52spr_unc_cha51uncore_cha_51spr_unc_cha50uncore_cha_50spr_unc_cha49uncore_cha_49spr_unc_cha48uncore_cha_48spr_unc_cha47uncore_cha_47spr_unc_cha46uncore_cha_46spr_unc_cha45uncore_cha_45spr_unc_cha44uncore_cha_44spr_unc_cha43uncore_cha_43spr_unc_cha42uncore_cha_42spr_unc_cha41uncore_cha_41spr_unc_cha40uncore_cha_40spr_unc_cha39spr_unc_cha38spr_unc_cha37spr_unc_cha36spr_unc_cha35spr_unc_cha34spr_unc_cha33spr_unc_cha32spr_unc_cha31spr_unc_cha30spr_unc_cha29spr_unc_cha28spr_unc_cha27spr_unc_cha26spr_unc_cha25spr_unc_cha24spr_unc_cha23spr_unc_cha22spr_unc_cha21spr_unc_cha20spr_unc_cha19spr_unc_cha18spr_unc_cha17spr_unc_cha16spr_unc_cha15spr_unc_cha14spr_unc_cha13spr_unc_cha12spr_unc_cha11spr_unc_cha10spr_unc_cha9spr_unc_cha8spr_unc_cha7spr_unc_cha6spr_unc_cha5spr_unc_cha4spr_unc_cha3spr_unc_cha2spr_unc_cha1spr_unc_cha0Direct GO opcodesHitMe Cache hitsHitMe Cache accessesHitMe Cache missesHitMe Cache updatesLLC Cache LookupsLLC cache victimsMemory ModesDDR Access (experimental)All from Local IACLFlush from Local IACRd from local IADRd Pref from local IAHits from Local IACRd hits from local IACRd Pref hits from local IAIA_HIT_CXL_ACCIA_HIT_CXL_ACC_LOCALDRd hits from local IADRd Pref hits from local IALLCPrefRFO hits from local IARFO Pref hits from local IALLCPrefData from local IALLCPrefRFO from local IAmisses from Local IACRd misses from local IAIA_MISS_CRDMORPH_CXL_ACCCRd Pref misses from local IAIA_MISS_CXL_ACCIA_MISS_CXL_ACC_LOCALDRd misses from local IAIA_MISS_DRDMORPH_CXL_ACCIA_MISS_DRD_CXL_ACCIA_MISS_DRD_CXL_ACC_LOCALIA_MISS_DRD_OPT_CXL_ACC_LOCALDRd Pref misses from local IAIA_MISS_DRD_PREF_CXL_ACCIA_MISS_LLCPREFCODE_CXL_ACCIA_MISS_LLCPREFDATA_CXL_ACCIA_MISS_LLCPREFRFO_CXL_ACCRFO misses from local IAIA_MISS_RFOMORPH_CXL_ACCIA_MISS_RFO_CXL_ACCIA_MISS_RFO_CXL_ACC_LOCALRFO pref misses from local IAIA_MISS_RFO_PREF_CXL_ACCRFO pref from local IASpecItoM from Local IAAll from local IOHits from local IOItoM hits from local IORFO hits from local IOItoM from local IOMisses from local IOItoM misses from local IORFO misses from local IORdCur from local IORFO from local IOWbMtoIs issued by IO DevicesLocal Targets (experimental)MMIOMMIO Access (experimental)Near Memory (experimental)Non Coherent (experimental)Remote Targets (experimental)REM_ALLREM_SNPSSNPS_FROM_REMPRQ Rejected (experimental)IA traffic (experimental)IO traffic (experimental)IO_EIO_FSIO_MIO_MESFAll Requests (experimental)CRd Requests (experimental)Data Reads (experimental)LOCAL_CODELOCAL_DATA_RDLOCAL_DMND_CODELOCAL_DMND_DATA_RDLOCAL_DMND_RFOLOCAL_FLUSH_INVLOCAL_LLC_PFLOCAL_PFLOCAL_PF_CODELOCAL_PF_DATA_RDLOCAL_PF_RFOLOCAL_RFOWrite Requests (experimental)REMOTE_CODEREMOTE_DATA_RDREMOTE_FLUSH_INVREMOTE_OTHERREMOTE_RFORemote Writes (experimental)Op is WbMtoE (experimental)Direct GO (experimental)gnr_unc_imc11gnr_unc_imc10gnr_unc_imc9gnr_unc_imc8gnr_unc_imc7gnr_unc_imc6gnr_unc_imc5gnr_unc_imc4gnr_unc_imc3gnr_unc_imc2gnr_unc_imc1gnr_unc_imc0UNC_M_CAS_COUNT_SCH0UNC_M_CAS_COUNT_SCH1UNC_M_POWERDOWN_CYCLESUNC_M_RDB_OCCUPANCY_SCH0UNC_M_RDB_OCCUPANCY_SCH1UNC_M_RPQ_OCCUPANCY_SCH0_PCH0UNC_M_RPQ_OCCUPANCY_SCH0_PCH1UNC_M_RPQ_OCCUPANCY_SCH1_PCH0UNC_M_RPQ_OCCUPANCY_SCH1_PCH1UNC_M_SELF_REFRESHUNC_M_WPQ_OCCUPANCY_SCH0_PCH0UNC_M_WPQ_OCCUPANCY_SCH0_PCH1UNC_M_WPQ_OCCUPANCY_SCH1_PCH0UNC_M_WPQ_OCCUPANCY_SCH1_PCH1ENTER_SUCCESSENTER_SUCCESS_CYCLESSCH0_RANK0SCH0_RANK1SCH0_RANK2SCH0_RANK3SCH1_RANK0SCH1_RANK1SCH1_RANK2SCH1_RANK3Intel Knights CornerkncBANK_CONFLICTSBRANCHES_MISPREDICTEDCODE_CACHE_MISSNumber of code page walksDATA_CACHE_LINES_WRITTEN_BACKNumber of data page walksDATA_READ_MISS_OR_WRITE_MISSDATA_READ_OR_WRITEEXEC_STAGE_CYCLESFE_STALLEDINSTRUCTIONS_EXECUTED_V_PIPEL1_DATA_HIT_INFLIGHT_PF1L1_DATA_PF1L1_DATA_PF1_DROPL1_DATA_PF1_MISSL1_DATA_PF2L2_CODE_READ_MISS_CACHE_FILLL2_CODE_READ_MISS_MEM_FILLL2_DATA_HIT_INFLIGHT_PF2L2_DATA_PF1_MISSL2_DATA_PF2L2_DATA_PF2_DROPL2_DATA_PF2_MISSL2_DATA_READ_MISS_CACHE_FILLL2_DATA_READ_MISS_MEM_FILLL2_DATA_WRITE_MISS_CACHE_FILLL2_DATA_WRITE_MISS_MEM_FILLL2_READ_HIT_EL2_READ_HIT_ML2 Read Hit M StateL2_READ_HIT_SL2 Read Hit S StateL2_READ_MISSL2_VICTIM_REQ_WITH_DATAL2_WRITE_HITLONG_CODE_PAGE_WALKLONG_DATA_PAGE_WALKMEMORY_ACCESSES_IN_BOTH_PIPESMICROCODE_CYCLESPIPELINE_AGI_STALLSPIPELINE_FLUSHESPIPELINE_SG_AGI_STALLSSNP_HITM_BUNITSnoop HITM in BUNITSNP_HITM_L2Snoop HITM in L2SNP_HIT_L2Snoop HIT in L2VPU_DATA_READVPU_DATA_READ_MISSVPU_DATA_WRITEVPU_DATA_WRITE_MISSVPU_ELEMENTS_ACTIVEVPU_INSTRUCTIONS_EXECUTEDVPU_STALL_REGIntel SilvermontslmDECODE_RESTRICTIONL2_REJECT_XQRejected L2 requests to XQRS_FULL_STALLRS fullLLC_RQSTSBR_MISP_INST_RETIREDMS_DECODEDMS decoderNO_ALLOC_CYCLESFront-end allocationRetired loads micro-opsCORE_REJECT_L2QREHABQMemory reference queueFetch stallsPage walkerD_SIDE_WALKS:I_SIDE_WALKSD_SIDE_CYCLESD_SIDE_WALKSNumber of D-side page walksD_SIDE_CYCLES:eI_SIDE_CYCLESNumber of I-side page walksI_SIDE_CYCLES:eICACHE_FILL_PENDING_CYCLESPREDECODE_WRONGMECMISPREDICTSRAT_STALLNON_RETURN_INDIND_CALLTAKEN_JCCPARTIAL_READPARTIAL_WRITEUC_IFETCHPF_L1_DATA_RDLD_BLOCK_ST_FORWARDLD_BLOCK_STD_NOTREADYST_SPLITSLD_SPLITSSTA_FULLANY_LDANY_STNumber of L2 cache missesNumber of L2 cache referencesLD_DCU_MISSLD_L2_HITLD_L2_MISSLD_DTLB_MISSLD_UTLB_MISSNumber of load uops retiredNumber of store uops retiredALL_TAKEN_BRANCHESREL_CALLCount any the machine clearsIntel TremonttmtIntel Knights MillknmIntel Knights LandingknlBR_MISP_RETIRED:ANYL2_REQUESTSL2_REQUESTS_REJECTRECYCLEQPARTIAL_READSPARTIAL_WRITESUC_CODE_READSFULL_STREAMING_STORESPF_SOFTWARECounts Software prefetchesCounts L1 data HW prefetchesPARTIAL_STREAMING_STORESCounts any requestDMND_CODE_RD:PF_L2_CODE_RDCounts any Read requestANY_PF_L2Counts any Prefetch requestsPF_L2_RFO:PF_L2_CODE_RDAccounts for any responseDDR_NEARDDR_FARMCDRAM_NEARMCDRAM_FARL2_HIT_NEAR_TILE_E_FL2_HIT_NEAR_TILE_ML2_HIT_FAR_TILE_E_FL2_HIT_FAR_TILE_MMCDRAML2_HIT_NEAR_TILEL2_HIT_FAR_TILEL1_MISS_LOADSL2_HIT_LOADSL2_MISS_LOADSDTLB_MISS_LOADSUTLB_MISS_LOADSCounts all nukesSCALAR_SIMDPACKED_SIMDadl_grtcpu_atomadl_glccpu_coreLD_HEADMEM_BOUND_STALLSMEM_SCHEDULER_BLOCKOCR0OCR1SERIALIZATIONTOPDOWN_BAD_SPECULATIONTOPDOWN_BE_BOUNDTOPDOWN_FE_BOUNDTOPDOWN_RETIRINGFPDIVIDIVBRANCH_DETECTBRANCH_RESTEERCISCFRONTEND_BANDWIDTHFRONTEND_LATENCYPREDECODEALLOC_RESTRICTIONSNON_MEM_SCHEDULERREGISTERREORDER_BUFFERFASTNUKENON_C01_MS_SCBCOREWB_M_ANY_RESPONSESTORE_LATENCYLD_BUFRSVST_BUFIFETCH_DRAM_HITIFETCH_L2_HITIFETCH_LLC_HITLOAD_DRAM_HITLOAD_L2_HITLOAD_LLC_HITMRN_NUKESLOWANY_AT_RETDTLB_MISS_AT_RETL1_BOUND_AT_RETL1_MISS_AT_RETOTHER_AT_RETPGWALK_AT_RETST_ADDR_AT_RET4K_ALIASMISS_CAUSED_WALKL2_REQUESTCycles with retired uop(s)Retirement slots usedRETIRING_SLOTSRetired load instructionsRetired store instructionsRetired NOP instructionsV5Total execution stallsLICENSE_1LICENSE_2LICENSE_3Return instructions retiredknm_unc_imc_uclk1uncore_mc_uclk_1knl_unc_imc_uclk1knm_unc_imc_uclk0uncore_mc_uclk_0knl_unc_imc_uclk0knm_unc_imc5knl_unc_imc5knm_unc_imc4knl_unc_imc4knm_unc_imc3knl_unc_imc3knm_unc_imc2knl_unc_imc2knm_unc_imc1knl_unc_imc1knm_unc_imc0knl_unc_imc0UNC_M_U_CLOCKTICKSIMC UCLK countsUNC_M_D_CLOCKTICKSIMC Uncore DCLK countsknm_unc_edc_eclk7uncore_edc_eclk_7knl_unc_edc_eclk7knm_unc_edc_eclk6uncore_edc_eclk_6knl_unc_edc_eclk6knm_unc_edc_eclk5uncore_edc_eclk_5knl_unc_edc_eclk5knm_unc_edc_eclk4uncore_edc_eclk_4knl_unc_edc_eclk4knm_unc_edc_eclk3uncore_edc_eclk_3knl_unc_edc_eclk3knm_unc_edc_eclk2uncore_edc_eclk_2knl_unc_edc_eclk2knm_unc_edc_eclk1uncore_edc_eclk_1knl_unc_edc_eclk1knm_unc_edc_eclk0uncore_edc_eclk_0knl_unc_edc_eclk0knm_unc_edc_uclk7uncore_edc_uclk_7knl_unc_edc_uclk7knm_unc_edc_uclk6uncore_edc_uclk_6knl_unc_edc_uclk6knm_unc_edc_uclk5uncore_edc_uclk_5knl_unc_edc_uclk5knm_unc_edc_uclk4uncore_edc_uclk_4knl_unc_edc_uclk4knm_unc_edc_uclk3uncore_edc_uclk_3knl_unc_edc_uclk3knm_unc_edc_uclk2uncore_edc_uclk_2knl_unc_edc_uclk2knm_unc_edc_uclk1uncore_edc_uclk_1knl_unc_edc_uclk1knm_unc_edc_uclk0uncore_edc_uclk_0knl_unc_edc_uclk0UNC_E_E_CLOCKTICKSUNC_E_RPQ_INSERTSUNC_E_WPQ_INSERTSUNC_E_U_CLOCKTICKSUNC_E_EDC_ACCESSMiss EMiss MMISS_INVALIDMiss IMISS_GARBAGEMiss Gknm_unc_cha37knl_unc_cha37knm_unc_cha36knl_unc_cha36knm_unc_cha35knl_unc_cha35knm_unc_cha34knl_unc_cha34knm_unc_cha33knl_unc_cha33knm_unc_cha32knl_unc_cha32knm_unc_cha31knl_unc_cha31knm_unc_cha30knl_unc_cha30knm_unc_cha29knl_unc_cha29knm_unc_cha28knl_unc_cha28knm_unc_cha27knl_unc_cha27knm_unc_cha26knl_unc_cha26knm_unc_cha25knl_unc_cha25knm_unc_cha24knl_unc_cha24knm_unc_cha23knl_unc_cha23knm_unc_cha22knl_unc_cha22knm_unc_cha21knl_unc_cha21knm_unc_cha20knl_unc_cha20knm_unc_cha19knl_unc_cha19knm_unc_cha18knl_unc_cha18knm_unc_cha17knl_unc_cha17knm_unc_cha16knl_unc_cha16knm_unc_cha15knl_unc_cha15knm_unc_cha14knl_unc_cha14knm_unc_cha13knl_unc_cha13knm_unc_cha12knl_unc_cha12knm_unc_cha11knl_unc_cha11knm_unc_cha10knl_unc_cha10knm_unc_cha9knl_unc_cha9knm_unc_cha8knl_unc_cha8knm_unc_cha7knl_unc_cha7knm_unc_cha6knl_unc_cha6knm_unc_cha5knl_unc_cha5knm_unc_cha4knl_unc_cha4knm_unc_cha3knl_unc_cha3knm_unc_cha2knl_unc_cha2knm_unc_cha1knl_unc_cha1knm_unc_cha0knl_unc_cha0UNC_H_U_CLOCKTICKSUNC_H_INGRESS_OCCUPANCYUNC_H_INGRESS_INSERTSUNC_H_INGRESS_INT_STARVEDCycles Internal StarvationISMQ RejectsISMQ retriesOther Queue RetriesUNC_H_SF_LOOKUPUNC_H_CACHE_LINES_VICTIMIZEDUNC_H_TOR_INSERTSUNC_H_TOR_OCCUPANCYUNC_H_MISCUNC_H_AG0_AD_CRD_ACQUIREDUNC_H_AG0_AD_CRD_ACQUIRED_EXTUNC_H_AG0_AD_CRD_OCCUPANCYUNC_H_AG1_AD_CRD_ACQUIREDUNC_H_AG1_AD_CRD_ACQUIRED_EXTUNC_H_AG1_AD_CRD_OCCUPANCYUNC_H_AG0_BL_CRD_ACQUIREDUNC_H_AG0_BL_CRD_ACQUIRED_EXTUNC_H_AG0_BL_CRD_OCCUPANCYUNC_H_AG1_BL_CRD_ACQUIREDUNC_H_AG1_BL_CRD_ACQUIRED_EXTUNC_H_AG1_BL_CRD_OCCUPANCYUNC_H_EGRESS_VERT_OCCUPANCYCMS Vert Egress Occupancy.UNC_H_EGRESS_VERT_INSERTSCMS Vert Egress Allocations.UNC_H_EGRESS_VERT_CYCLES_FULLUNC_H_EGRESS_VERT_CYCLES_NEUNC_H_EGRESS_VERT_NACKCMS Vertical Egress NACKs.UNC_H_EGRESS_VERT_STARVEDUNC_H_EGRESS_VERT_ADS_USEDCMS Vertical ADS Used.UNC_H_EGRESS_VERT_BYPASSCMS Vertical Egress Bypass.UNC_H_EGRESS_HORZ_OCCUPANCYUNC_H_EGRESS_HORZ_INSERTSUNC_H_EGRESS_HORZ_CYCLES_FULLUNC_H_EGRESS_HORZ_CYCLES_NEUNC_H_EGRESS_HORZ_NACKCMS Horizontal Egress NACKs.UNC_H_EGRESS_HORZ_STARVEDUNC_H_EGRESS_HORZ_ADS_USEDCMS Horizontal ADS Used.UNC_H_EGRESS_HORZ_BYPASSCMS Horizontal Egress Bypass.UNC_H_RING_BOUNCES_VERTUNC_H_RING_BOUNCES_HORZUNC_H_RING_SINK_STARVED_VERTUNC_H_RING_SINK_STARVED_HORZUNC_H_RING_SRC_THRTUNC_H_FAST_ASSERTEDUNC_H_VERT_RING_AD_IN_USEUNC_H_HORZ_RING_AD_IN_USEUNC_H_VERT_RING_AK_IN_USEUNC_H_HORZ_RING_AK_IN_USEUNC_H_VERT_RING_BL_IN_USEUNC_H_HORZ_RING_BL_IN_USEUNC_H_VERT_RING_IV_IN_USEUNC_H_HORZ_RING_IV_IN_USEUNC_H_EGRESS_ORDERINGUNC_H_TG_INGRESS_OCCUPANCYUNC_H_TG_INGRESS_INSERTSUNC_H_TG_INGRESS_BYPASSUNC_H_TG_INGRESS_CRD_STARVEDUNC_H_TG_INGRESS_BUSY_STARVEDIVFIV_SNP_GO_UPIV_SNP_GO_DNleftrightup - vertical - horizontal - AD ring - AK ring - BL ring - IV ringAD - Agent 0AK - Agent 0BL - Agent 0IV - Agent 0AD - Agent 1AK - Agent 1BL - Agent 1for Transgress 8ANY_OF_TGR0_THRU_TGR7for Transgress 0-7for Transgress 0for Transgress 1for Transgress 2for Transgress 3for Transgress 4for Transgress 5for Transgress 6for Transgress 7Silent Snoop EvictionWrite Combining Aliasing.CV0 Prefetch Victim.CV0 Prefetch Miss. -IRQ. -SF/LLC Evictions. -PRQ. -IPQ. -Hit (Not a Miss). -Miss.IRQ_HIT -IRQ HIT.IRQ_MISS -IRQ MISS.PRQ_HIT -PRQ HIT.PRQ_MISS -PRQ MISS.IPQ_HIT -IPQ HITIPQ_MISS -IPQ MISSANY_REJECTSF victimSF wayallow snoopPA matchAD RequestAD ResponseBL ResponseBL WBBL NCBBL NCSAK non upiIV non upiInternal starved with IRQ.Internal starved with IPQ.Internal starved with ISMQ.Internal starved with PRQ.knm_unc_m2pcieuncore_m2pcieknl_unc_m2pcieUNC_M2P_INGRESS_CYCLES_NEUNC_M2P_EGRESS_CYCLES_NEUNC_M2P_EGRESS_INSERTSUNC_M2P_EGRESS_CYCLES_FULLCBO_IDIIntel GoldmontglmRequests rejected by the XQISSUE_SLOTS_NOT_CONSUMEDLoads blocked (Precise Event)DL1Cycles a divider is busyMS decode startsRequests rejected by the L2Q DTLB_MISS_STORESAll machine clearsFULL_STRM_STFULL_STRM_ST:PARTIAL_STRM_STANY_PF_DATA_RDRequest: number of RFOResponse: any response typeSupplier: counts L2 hitsL2_MISS_HIT_OTHER_CORE_NO_FWDL2_MISS_HITM_OTHER_COREL2_MISS_SNP_NON_DRAML2_MISS_SNP_ANYMS_ENTRYDIRTY_EVICTIONWCB_HITL2 cache request missesRESOURCE_FULLRECOVERYLOAD_PAGE_SPLITSTORE_PAGE_SPLITcmplthrPentium4 (Prescott)netburst_pPentium4netburstcomplementedgeTC_deliver_modeBBIBBPU_fetch_requestTCMISSTrace cache lookup missITLB_referenceHIT_UCUncacheable ITLB hitmemory_cancelST_RB_FULL64K_CONFConflicts due to 64K aliasingmemory_completeLSCSSCAny split stores completedload_port_replaySPLIT_LDSplit loadstore_port_replaySPLIT_STSplit storeMOB_load_replayNO_STANO_STDPARTIAL_DATAUNALGN_ADDRpage_walk_typeDTMISSITMISSBSQ_cache_referenceRD_2ndL_HITSRD_2ndL_HITERD_2ndL_HITMRD_3rdL_HITSRD_3rdL_HITERD_3rdL_HITMRD_2ndL_MISSRead 2nd level cache missRD_3rdL_MISSRead 3rd level cache missWR_2ndL_MISSIOQ_allocationTYPE_BIT0Bus request type (bit 0)TYPE_BIT1Bus request type (bit 1)TYPE_BIT2Bus request type (bit 2)TYPE_BIT3Bus request type (bit 3)TYPE_BIT4Bus request type (bit 4)ALL_READCount read entriesALL_WRITECount write entriesMEM_UCMEM_WCMEM_WTMEM_WPMEM_WBIOQ_active_entriesFSB_data_activityDRDY_DRVDRDY_OWNDRDY_OTHERDBSY_DRVDBSY_OWNDBSY_OTHERBSQ_allocationREQ_TYPE0REQ_TYPE1REQ_LEN0REQ_LEN1REQ_IO_TYPEREQ_LOCK_TYPERequest type is bus lockREQ_CACHE_TYPERequest type is cacheableREQ_SPLIT_TYPEREQ_DEM_TYPEREQ_ORD_TYPERequest is an ordered typeMEM_TYPE0MEM_TYPE1MEM_TYPE2BSQ_active_entriesSSE_input_assistpacked_SP_uopTAG0TAG1TAG2TAG3packed_DP_uopscalar_SP_uopscalar_DP_uop64bit_MMX_uop128bit_MMX_uopx87_FP_uopCount all x87 FP uopsTC_miscNumber of flushesglobal_power_eventsRUNNINGtc_ms_xferA TC to MS transfer occurreduop_queue_writesFROM_TC_BUILDFROM_TC_DELIVERFROM_ROMretired_mispred_branch_typeConditional jumpsIndirect call branchesReturn branchesretired_branch_typeresource_stallSBFULLWC_BufferWCB_EVICTSWCB_FULL_EVICTb2b_cyclesBIT5BIT6bnrBIT7BIT8bit 8BIT9bit 9front_end_eventNBOGUSThe marked uops are not bogusThe marked uops are bogusexecution_eventNBOGUS0NBOGUS1NBOGUS2NBOGUS3replay_eventL1_LD_MISSL2_LD_MISSDTLB_LD_MISSDTLB_ST_MISSDTLB_ALL_MISSBR_MSPMOB_LD_REPLAYSP_LD_RETSP_ST_RETinstr_retiredNBOGUSNTAGNBOGUSTAGuops_retireduops_typeTAGLOADSThe uop is a load operationTAGSTORESThe uop is a store operationMMNPBranch not-taken predictedMMNMBranch not-taken mispredictedMMTPBranch taken predictedMMTMBranch taken mispredictedmispred_branch_retiredx87_assistFPSUHandle FP stack underflowFPSOHandle FP stack overflowPOAOHandle x87 output overflowPOAUHandle x87 output underflowPREAHandle x87 input assistmachine_clearMOCLEARSMCLEARinstr_completedNon-bogus instructionsBogus instructionsAMD64 K7amd64_k7DATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2DATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITL1 DTLB Miss and L2 DTLB HitL1_DTLB_AND_L2_DTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesCPU Clocks not HaltedINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissRETIRED_INSTRUCTIONSRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_TAKENInterrupts TakenExclusiveOwnedModifiedL2_INVALIDInvalid line from L2L2_SHAREDShared-state line from L2L2_EXCLUSIVEExclusive-state line from L2L2_OWNEDOwned-state line from L2L2_MODIFIEDModified-state line from L2AMD64 K8 RevGamd64_k8_revgAMD64 K8 RevFamd64_k8_revfAMD64 K8 RevEamd64_k8_reveAMD64 K8 RevDamd64_k8_revdAMD64 K8 RevCamd64_k8_revcAMD64 K8 RevBamd64_k8_revbDISPATCHED_FPUDispatched FPU OperationsCYCLES_NO_FPU_OPS_RETIREDDISPATCHED_FPU_OPS_FAST_FLAGSEGMENT_REGISTER_LOADSSegment Register LoadsLS_BUFFER_2_FULL_CYCLESLS Buffer 2 FullLOCKED_OPSLocked OperationsMEMORY_REQUESTSMemory Requests by TypeDATA_PREFETCHESData PrefetcherSYSTEM_READ_RESPONSESQUADWORDS_WRITTEN_TO_SYSTEMQuadwords Written to SystemREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_FILL_WRITEBACKL2 Fill/WritebackINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsRetired InstructionsRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRetired MMX/FP InstructionsDECODER_EMPTYDecoder EmptyDISPATCH_STALLSDispatch StallsDISPATCH_STALL_FOR_FPU_FULLDispatch Stall for FPU FullDISPATCH_STALL_FOR_LS_FULLDispatch Stall for LS FullFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesDRAM_ACCESSES_PAGEDRAM AccessesMEMORY_CONTROLLER_TURNAROUNDSMemory Controller TurnaroundsMEMORY_CONTROLLER_BYPASSSIZED_BLOCKSSized BlocksTHERMAL_STATUS_AND_ECC_ERRORSThermal Status and ECC ErrorsCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCKCache Block CommandsSIZED_COMMANDSSized CommandsGARTGART EventsHYPERTRANSPORT_LINK0HYPERTRANSPORT_LINK1HYPERTRANSPORT_LINK2COMMAND_DWORD_SENTCommand dword sentDATA_DWORD_SENTData dword sentBUFFER_RELEASE_DWORD_SENTBuffer release dword sentNOP_DWORD_SENTNop dword sent (idle)All sub-events selectedAPERTURE_HIT_FROM_CPUAPERTURE_HIT_FROM_IOGART missProbe missProbe hit cleanHIT_DIRTY_NO_MEMORY_CANCELHIT_DIRTY_WITH_MEMORY_CANCELUPSTREAM_WRITESUpstream writesNON_POSTED_WRITE_BYTENON_POSTED_WRITE_DWORDREAD_BYTE_4_BYTESREAD_DWORD_1_16_DWORDSREAD_MODIFY_WRITERdModWrVICTIM_WRITEBACKVictim Block (Writeback)DCACHE_LOAD_MISSSHARED_ICACHE_REFILLREAD_BLOCK_MODIFIEDREAD_TO_DIRTYI_O_TO_I_OI/O to I/OI_O_TO_MEMI/O to MemCPU_TO_I_OCPU to I/OCPU_TO_MEMCPU to MemTO_REMOTE_NODETo remote nodeTO_LOCAL_NODETo local nodeFROM_REMOTE_NODEFrom remote nodeFROM_LOCAL_NODEFrom local nodeCLKS_CPU_ACTIVECLKS_CPU_INACTIVECLKS_DIE_TEMP_TOO_HIGHCLKS_TEMP_THRESHOLD_EXCEEDEDDRAM_ECC_ERRORS32_BYTE_WRITES32-byte Sized Writes64_BYTE_WRITES64-byte Sized Writes32_BYTE_READS32-byte Sized Reads64_BYTE_READS64-byte Sized ReadsHIGH_PRIORITYLOW_PRIORITYDRAM_INTERFACEDRAM_QUEUEDRAM controller queue bypassCHIP_SELECTDIMM (chip select) turnaroundPage Hit, Miss, or ConflictX87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtrapsPOSITION_0With low op in position 0POSITION_1With low op in position 1POSITION_2With low op in position 2X87 instructionsMMX_AND_3DNOWMMX and 3DNow! instructionsPACKED_SSE_AND_SSE2SCALAR_SSE_AND_SSE2L2_FILLSL2_WRITEBACKSL2 Writebacks to system.IC fillTLB_WALKTLB page table walkInstructions, Data, TLB walkDC fillTLB fill (page table walks)Tag snoop requestCancelled requestAll non-cancelled requestsQUADWORD_WRITE_TRANSFERQuadword write transferExclusive, Modified, SharedCancelled prefetchesATTEMPTEDPrefetch attemptsStore (PrefetchW)NTA (PrefetchNTA)SCRUBBER_ERRORScrubber errorPIGGYBACK_ERRORPiggyback scrubber errorsRefill from SystemNON_CACHEABLEWRITE_COMBININGStreaming store (SS) requestsCYCLES_SPECULATIVE_PHASECYCLES_NON_SPECULATIVE_PHASEHSAll segmentsOPS_ADDAdd pipe opsOPS_MULTIPLYMultiply pipe opsOPS_STOREStore pipe opsOPS_ADD_PIPE_LOAD_OPSAdd pipe load opsOPS_MULTIPLY_PIPE_LOAD_OPSMultiply pipe load opsOPS_STORE_PIPE_LOAD_OPSStore pipe load opsAMD64 Fam10h Istanbulamd64_fam10h_istanbulAMD64 Fam10h Shanghaiamd64_fam10h_shanghaiAMD64 Fam10h Barcelonaamd64_fam10h_barcelonaRETIRED_SSE_OPERATIONSRetired SSE OperationsRETIRED_MOVE_OPSRetired Move OpsRETIRED_SERIALIZING_OPSRetired Serializing OpsFP_SCHEDULER_CYCLESSMIS_RECEIVEDSMIs ReceivedL1_DTLB_HITL1 DTLB HitINEFFECTIVE_SW_PREFETCHESGLOBAL_TLB_FLUSHESGlobal TLB FlushesMAB_REQUESTSMAB_WAIT_CYCLESOctwords Written to SystemINSTRUCTION_CACHE_VICTIMSInstruction Cache VictimsITLB_RELOADSITLB ReloadsITLB_RELOADS_ABORTEDITLB Reloads AbortedMEMORY_CONTROLLER_SLOT_MISSESThermal StatusMEMORY_CONTROLLER_REQUESTSMemory Controller RequestsHYPERTRANSPORT_LINK3READ_REQUEST_TO_L3_CACHERead Request to L3 CacheL3_CACHE_MISSESL3 Cache MissesL3_EVICTIONSL3 EvictionsPAGE_SIZE_MISMATCHESPage Size MismatchesRETIRED_X87_OPSIBS_OPS_TAGGEDIBS Ops TaggedLFENCE_INST_RETIREDLFENCE Instructions RetiredSFENCE_INST_RETIREDSFENCE Instructions RetiredMFENCE_INST_RETIREDMFENCE Instructions RetiredAdd/subtract opsMultiply opsDivide opsGUEST_LARGERMTRR_MISMATCHMTRR mismatch.HOST_LARGERANY_STATEALL_CORESAll coresREAD_BLOCK_EXCLUSIVEREAD_BLOCK_SHAREDREAD_BLOCK_MODIFYRead Block ModifyCommand DWORD sentData DWORD sentBuffer release DWORD sentNop DW sent (idle)ADDRESS_EXT_DWORD_SENTAddress DWORD sentPER_PACKET_CRC_SENTPer packet CRC sentSUBLINK_MASKSubLink MaskAddress extension DWORD sentREAD_SIZEDRead SizedWRITE_SIZEDWrite SizedVICTIM_BLOCKVictim BlockNODE_GROUP_SELECTLOCAL_TO_0_4From Local node to Node 0/4LOCAL_TO_1_5From Local node to Node 1/5LOCAL_TO_2_6From Local node to Node 2/6LOCAL_TO_3_7From Local node to Node 3/7Read blockRead block sharedRead block modifiedCHANGE_TO_DIRTYChange-to-DirtyLOCAL_TO_4From Local node to Node 4LOCAL_TO_5From Local node to Node 5LOCAL_TO_6From Local node to Node 6LOCAL_TO_7From Local node to Node 7LOCAL_TO_0From Local node to Node 0LOCAL_TO_1From Local node to Node 1LOCAL_TO_2From Local node to Node 2LOCAL_TO_3From Local node to Node 3WRITE_REQUESTSPREFETCH_REQUESTS32_BYTES_WRITES32 Bytes Sized Writes64_BYTES_WRITES64 Bytes Sized Writes32_BYTES_READS32 Bytes Sized Reads64_BYTES_READS64 Byte Sized ReadsREQUEST_HIT_TABLE_WALKDEV_HITDEV hitDEV_MISSDEV missDEV_ERRORDEV errorMULTIPLE_TABLE_WALKUpstream ISOC writesUPSTREAM_NON_ISOC_WRITESUpstream non-ISOC writesIO to IOIO to MemCPU to IOSTC_TRIP_POINTS_CROSSEDCLOCKS_HTC_P_STATE_INACTIVECLOCKS_HTC_P_STATE_ACTIVEDCT0 DCQ bypassDCT1 DCQ bypassDCT0 Read to write turnaroundDCT0 Write to read turnaroundDCT1_DIMMDCT1_READ_TO_WRITE_TURNAROUNDDCT1 Read to write turnaroundDCT1_WRITE_TO_READ_TURNAROUNDDCT1 Write to read turnaroundDCT0_COMMAND_SLOTS_MISSEDDCT0 Command Slots MissedDCT1_COMMAND_SLOTS_MISSEDDCT1 Command Slots MissedDCT0_PAGE_TABLE_OVERFLOWDCT0 Page Table OverflowDCT1_PAGE_TABLE_OVERFLOWDCT1 Page Table OverflowDCT0 Page hitDCT0 Page MissDCT0 Page ConflictDCT1_PAGE_HITDCT1 Page hitDCT1_PAGE_MISSDCT1 Page MissDCT1_PAGE_CONFLICTDCT1 Page Conflict4K_PAGE_FETCHES2M_PAGE_FETCHESHW_PREFETCH_FROM_DCHardware prefetch from DCOctword write transferDATA_ERRORData ErrorBuffer 0Buffer 2Buffer 3Buffer 4Buffer 5Buffer 6Buffer 7BUFFER_8Buffer 8BUFFER_9Buffer 9SW_PREFETCH_HIT_IN_L1SW_PREFETCH_HIT_IN_L2Software prefetch hit in L2.L1_4K_TLB_HITL1 4K TLB hitL1_2M_TLB_HITL1 2M TLB hitL1_1G_TLB_HITL1 1G TLB hitLOAD_PIPE_ERRORLoad pipe errorSTORE_WRITE_PIPE_ERRORStore write pipe error4K_TLB_RELOAD4K TLB reload2M_TLB_RELOAD2M TLB reload1G_TLB_RELOAD1G TLB reloadL2_4K_TLB_HITL2 4K TLB hitL2_2M_TLB_HITL2 2M TLB hitL2_1G_TLB_HITL2 1G TLB hitNOT_BY_PREFETCHNTARefill from the NorthbridgeSTORE_IS_SMALLER_THAN_LOADStore is smaller than load.MISALIGNEDMisaligned.CYCLES_WAITINGBOTTOM_EXECUTE_CYCLESBOTTOM_SERIALIZING_CYCLESSSE_BOTTOM_EXECUTING_UOPSSSE_BOTTOM_SERIALIZING_UOPSX87_BOTTOM_EXECUTING_UOPSX87_BOTTOM_SERIALIZING_UOPSLOW_QW_MOVE_UOPSHIGH_QW_MOVE_UOPSALL_OTHER_MERGING_MOVE_UOPSAll other merging move uopsALL_OTHER_MOVE_UOPSAll other move uopsSINGLE_ADD_SUB_OPSSINGLE_MUL_OPSSingle precision multiply opsSINGLE_DIV_OPSDOUBLE_ADD_SUB_OPSDOUBLE_MUL_OPSDouble precision multiply opsDOUBLE_DIV_OPSOP_TYPEOp type: 0=uops. 1=FLOPSAMD64 Fam11h Turionamd64_fam11h_turionDRAM_ACCESSESMEMORY_CONTROLLER_RBD_QUEUETHERMAL_STATUSDEVDEV EventsSIDEBAND_SIGNALSINTERRUPT_EVENTSInterrupt EventsADDRESS_DWORD_SENTUPSTREAM_ISOC_WRITESUpstream ISOC writes.Upstream non-ISOC writes.MEMHOT_L_ASSERTIONSHTC_TRANSITIONSPROCHOT_L_ASSERTIONSCOUNTER_REACHEDDCT0_READ_TO_WRITEDCT0_WRITE_TO_READDCT0 write-to-read turnaroundDCT0_DIMMDCT1_READ_TO_WRITEDCT1_WRITE_TO_READDCT1 write-to-read turnaroundDCT_PAGE_TABLE_OVERFLOWDCT Page Table OverflowSTALE_TABLE_ENTRY_HITSDCT0_PAGE_HITDCT0_PAGE_MISSDCT0_PAGE_CONFLICTWRITE_REQUESTWrite request.READ_REQUESTRead request.STOPGRANTSHUTDOWNFIXED_AND_LPAFixed and LPASMINMIINITSTARTUPEOIAMD64 Fam12h Llanoamd64_fam12h_llanoNORTHBRIDGE_READ_RESPONSESOCTWORDS_WRITTEN_TO_SYSTEMMEMORY_CONTROLLER_0_PAGEMEMORY_CONTROLLER_1_PAGEUPSTREAM_HIGH_PRIORITY_READSUpstream high priority reads.UPSTREAM_LOW_PRIORITY_READSUpstream low priority reads.UPSTREAM_LOW_PRIORITY_WRITESUpstream low priority writes.MEMHOT_L assertions.BANK_CLOSEDDCT0_RBDDCT0 RBD.DCT1_RBDDCT1 RBD.DCT0_PREFETCHDCT0 Prefetch.DCT1_PREFETCHDCT1 Prefetch.PAGE_TABLE_CLOSED_INACTIVITYDCT0_HITDCT0_MISSDCT0_CONFLICTSSE and SSE2 instructionsSMC_NO_INFLIGHTSMC_INFLIGHTOCTWORD_WRITE_TRANSFERCACHE_DISABLEDAMD64 Fam14h Bobcatamd64_fam14h_bobcatRETIRED_X87_FPU_OPSRSQ_FULLDATA_CACHE_REFILLS_FROM_NBDCACHE_SW_PREFETCHESMEMORY_CONTROLLER_PAGE_TABLEDEV_EVENTSInterrupt eventsPDC_MISSPDC missHOST_PDE_LEVELHost PDE levelHOST_PDPE_LEVELHost PDPE levelHOST_PML4E_LEVELHost PML4E levelGUEST_PDE_LEVELGuest PDE levelGUEST_PDPE_LEVELGuest PDPE levelGUEST_PML4E_LEVELGuest PML4E levelStopgrantShutdownWbinvdInvdUPSTREAM_HIGH_PRIO_READSUpstream high priority readsUPSTREAM_LOW_PRIO_READSUpstream low priority readsUPSTREAM_LOW_PRIO_WRITESMEMHOT_LMEMHOT_L assertionsHTC_TRANSITIONPROCHOT_LDCQ_BYPASS_MAXDCT0 RBDDCT0 prefetchDCT0_PAGE_TABLE_STALE_HITDCT0_PAGE_TABLE_IDLE_INCDCT0_PAGE_TABLE_IDLE_DECDCT0_PAGE_TABLE_CLOSEDWrite requestX87 or MMX instructionsINVALIDATING_LS_PROBEINVALIDATING_BU_PROBEIC_ATTR_WRITES_L2_ACCESSIC_ATTR_WRITES_L2_WRITESDIRTY_SUCCESSChange-to-dirty successUncacheableDC_BUFFER_0Data cache buffer 0DC_BUFFER_1Data cache buffer 1DC_BUFFER_2Data cache buffer 2DC_BUFFER_3Data cache buffer 3DC_BUFFER_4Data cache buffer 4DC_BUFFER_5Data cache buffer 5DC_BUFFER_6Data cache buffer 6DC_BUFFER_7Data cache buffer 7IC_BUFFER_0Instruction cache Buffer 1IC_BUFFER_1Instructions cache buffer 1ANY_IC_BUFFERAny instruction cache bufferANY_DC_BUFFERAny data cache bufferNO_MABSW prefetch hits L2STORES_L1TLB_MISSStores that miss L1TLBLOADS_L1TLB_MISSLoads that miss L1TLBSTORES_L2TLB_MISSStores that miss L2TLBLOADS_L2TLB_MISSLoads that miss L2TLBEviction from probeShared evictionExclusive evictionOwned evictionModified evictionUncacheable dataFrom non-cacheable dataFrom shared linesFrom exclusive linesFrom owned linesFrom modified linesUNLOCK_LINEMULT_OPSDIV_FSQRT_OPSDivide and fqsrt opsPipe 0 (fadd, imul, mmx) opsPipe 1 (fmul, store, mmx) opsPipe 1 and Pipe 0 opsAMD64 Fam15h NorthBridgeamd64_fam15h_nbamd_nbAMD64 Fam15h Interlagosamd64_fam15h_interlagosCACHE_BLOCK_COMMANDSGART_EVENTSCPU_REQUESTS_TO_TARGET_NODECPU Requests to Target NodeREQUEST_CACHE_STATUS_0Request Cache Status 0REQUEST_CACHE_STATUS_1Request Cache Status 1NON_CANCELED_L3_READ_REQUESTSNon-canceled L3 Read RequestsL3_LATENCYL3 LatencyL3_REQUEST_CYCLEL3 Request cycle count.L3_REQUESTL3 request count.Measure on Core0Measure on Core1Measure on Core2Measure on Core3CORE_4Measure on Core4CORE_5Measure on Core5CORE_6Measure on Core6CORE_7Measure on Core7ANY_COREMeasure on any coreCount prefetches onlyREAD_BLOCK_ANYCount any read requestWRITE_REQUESTS_TO_DCTREAD_REQUESTS_TO_DCTPREFETCH_REQUESTS_TO_DCT32_BYTES_SIZED_WRITES64_BYTES_SIZED_WRITES32_BYTES_SIZED_READS64_BYTE_SIZED_READSPROBE_HIT_SProbe Hit SPROBE_HIT_EProbe Hit EPROBE_HIT_MUW_OR_OProbe Hit MuW or OPROBE_HIT_MProbe Hit MProbe MissDIRECTED_PROBEDirected ProbeTRACK_CACHE_STAT_FOR_RDBLKMTrack Cache Stat for RdBlkMTRACK_CACHE_STAT_FOR_RDBLKTrack Cache Stat for RdBlkTRACK_CACHE_STAT_FOR_RDBLKSTrack Cache Stat for RdBlkSREAD_SIZED_LOCAL_TO_NODE_0WRITE_SIZED_LOCAL_TO_NODE_0VICTIM_BLOCK_LOCAL_TO_NODE_0READ_SIZED_LOCAL_TO_NODE_1WRITE_SIZED_LOCAL_TO_NODE_1VICTIM_BLOCK_LOCAL_TO_NODE_1READ_SIZED_LOCAL_TO_NODE_2WRITE_SIZED_LOCAL_TO_NODE_2VICTIM_BLOCK_LOCAL_TO_NODE_2READ_SIZED_LOCAL_TO_NODE_3WRITE_SIZED_LOCAL_TO_NODE_3VICTIM_BLOCK_LOCAL_TO_NODE_3READ_SIZED_LOCAL_TO_NODE_4WRITE_SIZED_LOCAL_TO_NODE_4VICTIM_BLOCK_LOCAL_TO_NODE_4READ_SIZED_LOCAL_TO_NODE_5WRITE_SIZED_LOCAL_TO_NODE_5VICTIM_BLOCK_LOCAL_TO_NODE_5READ_SIZED_LOCAL_TO_NODE_6WRITE_SIZED_LOCAL_TO_NODE_6VICTIM_BLOCK_LOCAL_TO_NODE_6READ_SIZED_LOCAL_TO_NODE_7WRITE_SIZED_LOCAL_TO_NODE_7VICTIM_BLOCK_LOCAL_TO_NODE_7ALL_LOCAL_TO_NODE_0_3ALL_LOCAL_TO_NODE_4_7READ_BLOCK_LOCAL_TO_NODE_4READ_BLOCK_LOCAL_TO_NODE_5READ_BLOCK_LOCAL_TO_NODE_6READ_BLOCK_LOCAL_TO_NODE_7READ_BLOCK_LOCAL_TO_NODE_0READ_BLOCK_LOCAL_TO_NODE_1READ_BLOCK_LOCAL_TO_NODE_2READ_BLOCK_LOCAL_TO_NODE_3COMMAND_DW_SENTCommand DW sentDATA_DW_SENTData DW sentBUFFER_RELEASE_DW_SENTBuffer release DW sentNOP_DW_SENTNOP DW sent (idle)ADDRESS_DW_SENTSUBLINK_1SUBLINK_0GART_MISSPROBE_HIT_CLEANUPSTREAM_NON-ISOC_WRITESNON-POSTED_SZWR_BYTENON-POSTED_SZWR_DWSZRD_BYTESZRD_DWREMOTE_IO_TO_LOCAL_IORemote IO to Local IOREMOTE_CPU_TO_LOCAL_IORemote CPU to Local IOLOCAL_IO_TO_REMOTE_IOLocal IO to Remote IOLOCAL_IO_TO_REMOTE_MEMLocal IO to Remote MemLOCAL_CPU_TO_REMOTE_IOLocal CPU to Remote IOLOCAL_CPU_TO_REMOTE_MEMLocal CPU to Remote MemLOCAL_IO_TO_LOCAL_IOLocal IO to Local IOLOCAL_IO_TO_LOCAL_MEMLocal IO to Local MemLOCAL_CPU_TO_LOCAL_IOLocal CPU to Local IOLOCAL_CPU_TO_LOCAL_MEMLocal CPU to Local MemNUM_HTC_TRIP_POINT_CROSSEDNUM_CLOCKS_HTC_PSTATE_ACTIVEDCT0_DCQ_BYPASSDCT1_DCQ_BYPASSDCT0_DIMM_TURNAROUNDDCT0_READ_WRITE_TURNAROUNDDCT0_WRITE_READ_TURNAROUNDDCT1_DIMM_TURNAROUNDDCT1_READ_WRITE_TURNAROUNDDCT1_WRITE_READ_TURNAROUNDDISPATCHED_FPU_OPSFPU Pipe AssignmentCYCLES_FPU_EMPTYFP Scheduler EmptyRETIRED_SSE_OPSRetired SSE/BNI OpsMOVE_SCALAR_OPTIMIZATIONBOTTOM_EXECUTE_OPLOAD_Q_STORE_Q_FULLLoad Queue/Store Queue FullCANCELLED_STORE_TO_LOADUNIFIED_TLB_HITUnified TLB HitUNIFIED_TLB_MISSUnified TLB MissDATA_PREFETCHERMAB_REQSMAB RequestsMAB_WAITMAB Wait CyclesOCTWORD_WRITE_TRANSFERSL2_CACHE_FILL_WRITEBACKPAGE_SPLINTERINGPage SplinteringL1 ITLB Miss, L2 ITLB HitL1 ITLB Miss, L2 ITLB MissINSTRUCTION_CACHE_INVALIDATEDRETIRED_MMX_FP_INSTRUCTIONSDISPATCH_STALL_FOR_LDQ_FULLDispatch Stall for LDQ FullDR0_BREAKPOINTSDR0 Breakpoint MatchDR1_BREAKPOINTSDR1 Breakpoint MatchDR2_BREAKPOINTSDR2 Breakpoint MatchDR3_BREAKPOINTSDR3 Breakpoint MatchTagged IBS OpsLS_DISPATCHLS DispatchEXECUTED_CLFLUSH_INSTRUCTIONSExecuted CLFLUSH InstructionsL2_PREFETCHER_TRIGGER_EVENTSL2 Prefetcher Trigger EventsDISPATCH_STALL_FOR_STQ_FULLDispatch Stall for STQ FullLOAD_OP_STORESLoad-op-StoresNumber of ops tagged by IBSIGNOREDTOTAL_FAULTSTotal microfaultsTOTAL_TRAPSTotal microtrapsINT2EXT_FAULTSInt2Ext faultsEXT2INT_FAULTSExt2Int faultsBYPASS_FAULTSBypass faultsMMX(tm) instructionsNON_SMC_PROBE_MISSNON_SMC_PROBE_HIT1G_PAGE_FETCHESL2 fills from systemL2_WRITEBACKS_CLEANL2 Clean Writebacks to systemL2 Cache Prefetcher requestNB probe requestCanceled requestL2 cache prefetcher requestOW write transferMODIFIED_UNWRITTENModified unwrittenBUFFER_BIT_0Buffer entry index bit 0BUFFER_BIT_1Buffer entry index bit 1BUFFER_BIT_2Buffer entry index bit 2BUFFER_BIT_3Buffer entry index bit 3BUFFER_BIT_4Buffer entry index bit 4BUFFER_BIT_5Buffer entry index bit 5BUFFER_BIT_6Buffer entry index bit 6BUFFER_BIT_7Buffer entry index bit 74K_DATA2M_DATA1GB_DATA4K_INST2M_INST1G_INST4 KB unified TLB hit for data2 MB unified TLB hit for data1G_DATA1 GB unified TLB hit for dataPOISONFill with poison dataREAD_ERRORFill with read data errorDC_MISS_STREAMING_STORESIZE_ADDRESS_MISMATCHESLOAD_QUEUESTORE_QUEUESSE_RETIREDSSE_MISPREDICTEDX87_RETIREDX87_MISPREDICTEDSSE_MOVE_OPSNumber of SSE Move OpsSSE_MOVE_OPS_ELIMOPT_CANDSCALAR_OPS_OPTIMIZEDSINGLE_MUL_ADD_OPSDOUBLE_MUL_ADD_OPSOPS_PIPE0OPS_PIPE1OPS_PIPE2OPS_PIPE3OPS_DUAL_PIPE0OPS_DUAL_PIPE1OPS_DUAL_PIPE2OPS_DUAL_PIPE3AMD64 Fam17h Zen2amd64_fam17h_zen2AMD64 Fam17h Zen1amd64_fam17h_zen1amd64_fam17hL1_ITLB_MISS_L2_ITLB_HITL1_ITLB_MISS_L2_ITLB_MISSRETIRED_SSE_AVX_FLOPSDIV_CYCLES_BUSY_COUNTDIV_OP_COUNTNumber of divide uops.RETIRED_FUSED_INSTRUCTIONSInstructions Retired.TAGGED_IBS_OPSL2_PREFETCH_HIT_L2L2_PREFETCH_HIT_L3L2_PREFETCH_MISS_L3REQUESTS_TO_L2_GROUP1REQUESTS_TO_L2_GROUP2BAD_STATUS_2INEFFECTIVE_SOFTWARE_PREFETCHL1_DTLB_MISSL1 Data TLB misses.RETIRED_LOCK_INSTRUCTIONSSMI_RECEIVEDINTERRUPT_TAKENMAB_ALLOCATION_BY_PIPEMISALIGNED_LOADSMisaligned loads retiredNumber of TLB flushesSTORE_TO_LOAD_FORWARDSTORE_COMMIT_CANCELS_2L1_BTB_CORRECTIONL2_BTB_CORRECTIONDYNAMIC_INDIRECT_PREDICTIONSDECODER_OVERRIDE_BRANCH_PREDUOPS_QUEUE_EMPTYUOPS_DISPATCHED_FROM_DECODERFP_DISPATCH_FAULTSX87_FILL_FAULTx87 fill faultsXMM_FILL_FAULTXMM fill faultsYMM_FILL_FAULTYMM fill faultsYMM_SPILL_FAULTYMM spill faultsAny FP dispatch faultsAddition/subtraction FLOPSMultiplication FLOPSDivision FLOPS.X87_CTRL_RETX87_BOT_RETSSE_CTRL_RETSSE_BOT_RETALU_TOKEN_STALLINT_PHY_REG_FILE_RSRC_STALLLOAD_QUEUE_RSRC_STALLSTORE_QUEUE_RSRC_STALLINT_SCHEDULER_MISC_RSRC_STALLFP_REG_FILE_RSRC_STALLFP_SCHEDULER_FILE_RSRC_STALLFP_MISC_FILE_RSRC_STALLOPCACHE_DISPATCHEDPREFETCH_T0_T1_T2Any prefetchTLB_PIPE_EARLYhw_pfTLB_PIPE_LATEST_PIPEDATA_PIPETLB_RELOAD_1G_L2_MISSTLB_RELOAD_2M_L2_MISSTLB_RELOAD_4K_L2_MISSTLB_RELOAD_1G_L2_HITTLB_RELOAD_2M_L2_HITTLB_RELOAD_COALESCED_PAGE_HITTLB_RELOAD_4K_L2_HITWCB_FULLMABRESP_LCL_L2Fill from local L2.LS_MABRESP_LCL_CACHELS_MABRESP_LCL_DRAMLS_MABRESP_RMT_CACHELS_MABRESP_RMT_DRAMMAB_MCH_CNTDATA_PIPE_SW_PF_DC_HITLD_ST_DISPATCHSTORE_DISPATCHLD_DISPATCHLoad uops dispatched.ANY TLB flush.CACHEABLE_LOCKSNumber of bus locksSTLI_OTHERLS_RD_SIZEDLS_RD_SIZED_N_CIC_RD_SIZEDIC_RD_SIZED_N_CSMC_INVALBUS_LOCKS_ORIGINATORNumber of bus locks.BUS_LOCKS_RESPONSESNumber of bus lock responses.RD_BLK_LNumber of data cache storesLS_RD_BLK_C_SCACHEABLE_IC_READCHANGE_TO_XPREFETCH_L2Any L2 prefetch requestsLS_RD_BLK_L_HIT_XLS_RD_BLK_L_HIT_SLS_RD_BLK_XLS_RD_BLK_CIC_FILL_HIT_XIC_FILL_HIT_SIC_FILL_MISSIBS_COUNT_ROLLOVERIBS_TAGGED_OPS_RETIBS_TAGGED_OPSNumber of uops tagged by IBS.SSE_INSTRMMX_INSTRNumber of MMX instructions.X87_INSTRNumber of X87 instructions.IF1GIF2MIF4KRETIRED_SSE_AVX_OPERATIONSFP_SCHEDULER_EMPTYFPU_PIPE_ASSIGNMENTINSTRUCTION_PIPE_STALLL2_LATENCYLS_TO_L2_WBC_REQUESTSTABLEWALKER_ALLOCATIONDECODER_OVERRIDES_PREDICTIONLS_MABRESP_LCL_RMT_CACHELS_MABRESP_LCL_RMT_DRAMRETIRE_TOKEN_STALLRetire tokens unavailableAGSQ_TOKEN_STALLAGSQ tokens unavailableALU tokens unavailableALSQ3_0_TOKEN_STALLALSQ3_TOKEN_STALLALSQ3 tokens unavailableALSQ2_TOKEN_STALLALSQ2 tokens unavailableALSQ1_TOKEN_STALLALSQ1 tokens unavailableOC_IC_MODE_SWITCHIC_OC_MODE_SWITCHALLOC_ISIDE1ALLOC_ISIDE0ALLOC_DSIDE1ALLOC_DSIDE0PREFETCH_NTANon-temporal prefetches.STORE_PREFETCH_WLOAD_PREFETCH_WSPEC_LOCK_MAP_COMMITNON_SPEC_LOCKLoad/Store uops dispatched.WCB_WRITEWCB_CLOSECACHE_LINE_FLUSHI_LINE_FLUSHZERO_BYTE_STORELOCAL_IC_CLRC_L_ZEROOTHER_REQUESTSL2_CYCLES_WAITING_ON_FILLSL2_FILL_BUSYLoad/Store ReadBlock C/S hitIcache fill hit eXclusive.Icache fill hit Shared.Icache fill miss.IC_STALL_ANYIC_STALL_DQ_EMPTYIC_STALL_BACK_PRESSUREL2_INVALIDATING_PROBEFILL_INVALIDATEDDUAL3DUAL2DUAL1DUAL0TOTAL3TOTAL2TOTAL1TOTAL0DIV_SQR_R_OPSDivide and square root opsMultiple opsDP_MULT_ADD_FLOPSDP_DIV_FLOPSDP_MULT_FLOPSDP_ADD_SUB_FLOPSSP_MULT_ADD_FLOPSSP_DIV_FLOPSSP_MULT_FLOPSSP_ADD_SUB_FLOPSOPT_POTENTIALSSE_MOV_OPS_ELIMSSE_MOV_OPSNumber of SSE move ops.AMD64 Fam16h Jaguaramd64_fam16hRetired SSE/AVX OperationsRETIRED_X87_OPERATIONSRetired x87 operationsCOMMAND_RELATED_UNCACHABLECOMMAND_RELATED_READ_BLOCKCOMMAND_RELATED_DIRTYData PrefetchesMiss address buffer requestsSYSTEM_RESPONSESDATA_WRITTEN_TO_SYSTEMCACHE_CROSS_INVALIDATESNumber of PDC missesITLB reloads abortedRETIRED_INDIRECT_BRANCH_INFORetired indirect branch infoRETIRED_MISPREDICTED_TAKENOps tagged by IBSTAGGED_IBS_OPS_RETIREDIC_INVALIDATE_LS_PROBEIC_INVALIDATE_BU_PROBEHost: PDE levelHost: PDPE levelHost: PML4E levelGuest: PDE levelGuest: PDPE levelGuest: PML4E levelDC_INVALIDATES_ICDC_INVALIDATES_DCCD or WBINVDIC_INVALIDATES_ICIC_INVALIDATES_DC_DIRTYIC_HITS_DC_CLEAN_LINEReading codeDC_PROBE_REJECTED_EARLYDC probe rejected earlyDC_PROBE_REJECTED_LATEDC probe rejected lateDATA_LINE_EVICTIONSData line evictionsBYTE_ENABLE_MASK_UNCACHEABLEDATA_FOR_UNCACHEABLEDATA_FOR_WRITE_COMBINECHANGE_DIRTYChange to dirty successDC_MISS0Data cache miss buffer 0DC_MISS1Data cache miss buffer 1DC_MISS2Data cache miss buffer 2DC_MISS3Data cache miss buffer 3DC_MISS4Data cache miss buffer 4DC_MISS5Data cache miss buffer 5DC_MISS6Data cache miss buffer 6DC_MISS7Data cache miss buffer 7IC_MISS0IC_MISS1DC_ANYAny data cache miss bufferIC_ANYHits on MABChange to dirtyRDBLKMODRdBlkModREAD_BLOCK_SPECRead block speculativeREAD_BLOCK_SPEC_MODREAD_BLOCK_SPEC_SHAREDRead block speculative sharedREAD_BYTERead byteREAD_DOUBLEWORDRead doublewordWrite byteWRITE_DOUBLEWORDWrite doublewordSW_PREFETCH_DATA_CACHESW_PREFETCH_PENDING_FILLSW_PREFETCH_MABSW_PREFETCH_HIT_L2MISALIGN_16BMISALIGN_4KBSTORES_L1TLBLOADS_L1TLBSTORES_L2TLBLOADS_L2TLBEvicted from probeNON_CACHABLEnon-cachableNon-cachableThe number of loadsThe number of storesThe number of load-op-storesCYCLES_TO_ACQUIRECYCLES_TO_UNLOCKINVALIDATING_PROBESEvictions caused by fillsADD_AND_SUBAdd and subtractMultiplyDIVIDE_AND_FSQRTDivide and fsqrtSSE_CONTROL_RENAMING_UOPSX87_CONTROL_RENAMING_UOPSPipe0 dispatchesPipe1 dispatchesAMD64 Fam19h Zen4amd64_fam19h_zen4AMD64 Fam19h Zen3amd64_fam19h_zen3RETIRED_X87_FP_OPSRETIRED_FP_OPS_BY_WIDTHRETIRED_FP_OPS_BY_TYPERETIRED_INT_OPSPACKED_FP_OPS_RETIREDPACKED_INT_OPS_RETIREDMAB_ALLOCATION_BY_TYPEL1 Data TLB missesALLOC_MAB_COUNTP0_FREQ_CYCLES_NOT_IN_HALTL1_ITLB_FETCH_HITIC_TAG_HIT_MISSOP_CACHE_HIT_MISSDISPATCH_STALLS_1DISPATCH_STALLS_2RETIRED_OPSNumber of macro-ops retiredNumber of divide opsCYCLES_NO_RETIRERETIRED_UCODE_INSTRUCTIONSRETIRED_UCODE_OPSCounts Op IBS related eventsAll L2 cache requestsNOT_COMPLETE_LOAD_AND_ALUNOT_COMPLETE_MISSING_LOADTHREAD_NOT_SELECTEDFE_NO_OPSBE_STALLSSMT_CONTENTIONP0_FREQ_CYCLESFP128_ADDFP128_SUBFP128_MULFP128_MACFP128_DIVFP128_SQRTFP128_CMPFP128_CVTFP128_BLENDFP128_SHUFFLEFP128_LOGICALFP128_OTHERFP128_ALLFP256_ADDFP256_SUBFP256_MULFP256_MACFP256_DIVFP256_SQRTFP256_CMPFP256_CVTFP256_BLENDFP256_SHUFFLEFP256_LOGICALFP256_OTHERFP256_ALLINT128_ADDINT128_SUBINT128_MULINT128_MACINT128_AESINT128_SHAINT128_CMPINT128_CLMINT128_SHIFTINT128_MOVINT128_SHUFFLEINT128_PACKINT128_LOGICALINT128_OTHERINT128_ALLINT256_ADDINT256_SUBINT256_MULINT256_MACINT256_CMPINT256_SHIFTINT256_MOVINT256_SHUFFLEINT256_PACKINT256_LOGICALINT256_OTHERINT256_ALLNumber of add/subtract opsNumber of multiply opsDIV_SQRT_OPSL2_STREAML2_NEXT_LINEL2_UP_DOWNL2_BURSTL2_STRIDEL1_STREAML1_STRIDEL1_REGIONPREFETCH_L2_CMDNumber of MMX instructionsNumber of x87 instructionsINT_SCHEDULER_0_TOKEN_STALLINT_SCHEDULER_1_TOKEN_STALLINT_SCHEDULER_2_TOKEN_STALLINT_SCHEDULER_3_TOKEN_STALLFP_SCHEDULER_RSRC_STALLFP_FLUSH_RECOVERY_STALLFP_DISPATCHAny FP dispatchINTEGER_DISPATCHAny Integer dispatchOPCACHELOOP_BUFFEROC_HITOp cache hitOC_MISSOp cache missALL_OC_ACCESSAll op cache accessesIC_HITInstruction cache hitIC_MISSInstruction cache missALL_IC_ACCESSCOALESCED4KAny TLB flushMA4KMA64LOCAL_CCXNEAR_CACHE_NEAR_FARDRAM_IO_NEARFAR_CACHE_NEAR_FARDRAM_IO_FARALT_MEM_NEAR_FARFill from Extension MemoryLoad store allocationsAll allocationsStore ops dispatchedLoad ops dispatchedMMX_ADDNumber of MMX ADD ops retiredMMX_SUBNumber of MMX SUB ops retiredMMX_MULNumber of MMX MUL ops retiredMMX_MACNumber of MMX MAC ops retiredMMX_CMPNumber of MMX CMP ops retiredMMX_SHIFTMMX_MOVNumber of MMX MOV ops retiredMMX_SHUFFLEMMX_PACKMMX_LOGICALMMX_OTHERMMX_ALLAny MMX ops retiredSSE_AVX_ADDSSE_AVX_SUBSSE_AVX_MULSSE_AVX_MACSSE_AVX_AESSSE_AVX_SHASSE_AVX_CMPSSE_AVX_CLMSSE_AVX_SHIFTSSE_AVX_MOVSSE_AVX_SHUFFLESSE_AVX_PACKSSE_AVX_LOGICALSSE_AVX_OTHERSSE_AVX_ALLAny SSE/AVX ops retiredSCALAR_ADDSCALAR_SUBSCALAR_MULSCALAR_MACSCALAR_DIVSCALAR_SQRTSCALAR_CMPSCALAR_CVTSCALAR_BLENDSCALAR_OTHERSCALAR_ALLVECTOR_ADDVECTOR_SUBVECTOR_MULVECTOR_MACVECTOR_DIVNumber of DIV ops retiredVECTOR_SQRTVECTOR_CMPVECTOR_CVTVECTOR_BLENDVECTOR_SHUFFLEVECTOR_LOGICALVECTOR_OTHERVECTOR_ALLX87_UOPS_RETIREDX87 uops retiredMMX_UOPS_RETIREDMMX uops retiredSCALAR_UOPS_RETIREDScalar uops retiredPACK128_UOPS_RETIREDPacked 128-bit uops retiredPACK256_UOPS_RETIREDPacked 256-bit uops retiredPACK512_UOPS_RETIREDPacked 512-bit uops retiredDivision/Square-root FLOPSBFLOAT_MAC_FLOPSL2_HW_PREFETCHERL1_HW_PREFETCHERFP_DISP_IBS_MODEINT_DISP_IBS_MODEFP_DISP_RETIRE_MODEINT_DISP_RETIRE_MODEX86DECODER_DISPATCHEDINT_CACHEEXT_CACHE_LCLMEM_IO_LCLEXT_CACHE_RMTMEM_IO_RMTAMD64 RAPLamd64_raplAMD64 Fam19h Zen3 L3amd64_fam19h_zen3_l3amd_l3UNC_L3_REQUESTSUNC_L3_MISS_LATENCYUNC_L3_MISSESNumber of L3 cache missesAll types of requestsAMD64 Fam1Ah Zen5amd64_fam1ah_zen5WRITE_COMBINING_BUFFER_CLOSEBP_CORRECTIONBP_REDIRECTSFETCH_IBS_EVENTSL2_FILL_RESPONSE_SRCNEAR_FAR_CACHE_NEARNEAR_FAR_CACHE_FARL1_DC_HW_PFL1_DC_L2_HW_PFWrite combining buffer closeLS_RD_SIZED_NCAL_TOKEN_STALLAG_TOKEN_STALLEX_FLUSH_STALLSAMPLE_VALSAMPLE_FILTEREDSAMPLE_DISCARDEDFETCH_TAGGEDEX_REDIRRESYNCAll TLB FlushesFULL_LINE_64BOLDER_ST_VISIBLE_CANCELNumber of all locksINT128_NONEDo not count 128-bit opsINT128_CVTINT128_VNNIINT256_NONEDo not count 256-bit opsINT256_AESINT256_SHAINT256_CVTINT256_VNNIFP128_NONEDo not count any 128-bit opsFP128_MOVFP128_BFLOATFP256_NONEDo not count any 256-bit opsFP256_MOVFP256_BFLOATMMX_NONEDo count MMX opsMMX_AESNumber of MMX AES ops retiredMMX_SHANumber of MMX SHA ops retiredMMX_CVTMMX_VNNISSE_AVX_NONEDo not count SSE/AVX opsSSE_AVX_CVTSSE_AVX_VNNISCALAR_NONEDo not count scalar opsSCALAR_MOVESCALAR_SHUFFLESCALAR_BFLOATSCALAR_LOGICALVECTOR_NONEDo not count vector opsVECTOR_MOVEVECTOR_BFLOATALL_TYPEAll typesFLOP_TYPE_BFLOAT16B Float 16FLOP_TYPE_SCALAR_SINGLEScalar singleFLOP_TYPE_PACKED_SINGLEPacked singleFLOP_TYPE_SCALAR_DOUBLEScalar doubleFLOP_TYPE_PACKED_DOUBLEPacked doubleAMD64 Fam1ah Zen5 L3amd64_fam1ah_zen5_l3L3 hit%s (%s.%d): %d %d %d %d %d %s
%s (%s.%d): cannot mix raw umask with umask
%s (%s.%d): PMU %s does not support RAW umasks
%s (%s.%d): raw umask (%s) is not a number
%s (%s.%d): cannot find attribute %s
%s (%s.%d): too many attributes
%s (%s.%d): pfmlib_check_struct: user size too small %zu
%s (%s.%d): pfmlib_check_struct: invalid extra bits
%s (%s.%d): OS layer %s activated
%s (%s.%d): default OS layer: %s
%s (%s.%d): too many events for %s
%s (%s.%d): max encoding too high (%d > %d) for %s
%s (%s.%d): %s PMU not exported by OS
%s (%s.%d): %d PMU detected out of %d supported
%s (%s.%d): %s PMU blacklisted, skipping initialization
%s (%s.%d): %d %d RAW_UMASK (0x%x)
%s (%s.%d): PMU %s does not support PFM_OS_NONE
pmu: %s :: initialization failed
pmu: %s :: max encoding too high
pmu: %s :: missing pmu_detect callback
pmu: %s :: missing get_event_first callback
pmu: %s :: missing get_event_next callback
pmu: %s :: missing get_event_info callback
pmu: %s :: missing get_event_attr_info callback
pmu: %s :: no os event encoding callback
pmu: %s :: max_encoding is zero
invalid combination of model specific featurespmu: %s event%d: :: no name (prev event was %s)
pmu: %s event%d: %s :: no description
pmu: %s event%d: %s :: invalid type
pmu: %s event%d: %s :: numasks too big (<%d)
pmu: %s event%d: %s :: overflow umask idx defined but not needed (<%d)
pmu: %s event%d: %s :: ngrp cannot be zero
pmu: %s event%d: %s :: ngrp must be zero
pmu: %s event%d: %s umask%d :: no name
pmu: %s event%d:%s umask%d: %s :: no description
pmu: %s event%d: %s umask%d: %s :: invalid grpid %d (must be < %d)
pmu: %s event%d: %s :: numasks (%d) invalid more events exists
/proc/sys/kernel/perf_event_paranoid/proc/sys/kernel/perf_counter_paranoid%s (%s.%d): no default found for event %s unit mask group %d
%s (%s.%d): added default %s for group %d
%s (%s.%d): unsupported event type=%d
%s (%s.%d): perf::%s not available
%s (%s.%d): cloning static event table
%s (%s.%d): no core CPU PMU, going with default
%s (%s.%d): guessing plm from %s PMU plm=0x%x
issue slots per logical CPU (used for topdown toplevel computation, must be first event in the group)topdown useful slots retiring uops (must be used in a group with the other topdown- events with slots as leader)topdown wasted slots due to bad speculation (must be used in a group with the other topdown- events with slots as leader)topdown wasted slots due to frontend (must be used in a group with the other topdown- events with slots as leader)topdown wasted slots due to backend (must be used in a group with the other topdown- events with slots as leader)PERF_COUNT_HW_CACHE_REFERENCESPERF_COUNT_HW_BRANCH_INSTRUCTIONSPERF_COUNT_HW_STALLED_CYCLES_FRONTENDPERF_COUNT_HW_STALLED_CYCLES_BACKENDPERF_COUNT_SW_CONTEXT_SWITCHESPERF_COUNT_HW_CACHE_L1D:READ:ACCESSPERF_COUNT_HW_CACHE_L1D:READ:MISSPERF_COUNT_HW_CACHE_L1D:WRITE:ACCESSPERF_COUNT_HW_CACHE_L1D:WRITE:MISSPERF_COUNT_HW_CACHE_L1D:PREFETCH:ACCESSPERF_COUNT_HW_CACHE_L1D:PREFETCH:MISSPERF_COUNT_HW_CACHE_L1I:READ:ACCESSPERF_COUNT_HW_CACHE_L1I:READ:MISSPERF_COUNT_HW_CACHE_L1I:PREFETCH:ACCESSPERF_COUNT_HW_CACHE_L1I:PREFETCH:MISSLast level cache load accessesPERF_COUNT_HW_CACHE_LL:READ:ACCESSPERF_COUNT_HW_CACHE_LL:READ:MISSLast level cache store accessesPERF_COUNT_HW_CACHE_LL:WRITE:ACCESSPERF_COUNT_HW_CACHE_LL:WRITE:MISSLast level cache prefetch accessesPERF_COUNT_HW_CACHE_LL:PREFETCH:ACCESSLast level cache prefetch missesPERF_COUNT_HW_CACHE_LL:PREFETCH:MISSData Translation Lookaside BufferPERF_COUNT_HW_CACHE_DTLB:READ:ACCESSPERF_COUNT_HW_CACHE_DTLB:READ:MISSPERF_COUNT_HW_CACHE_DTLB:WRITE:ACCESSPERF_COUNT_HW_CACHE_DTLB:WRITE:MISSPERF_COUNT_HW_CACHE_DTLB:PREFETCH:ACCESSPERF_COUNT_HW_CACHE_DTLB:PREFETCH:MISSInstruction Translation Lookaside BufferPERF_COUNT_HW_CACHE_ITLB:READ:ACCESSPERF_COUNT_HW_CACHE_ITLB:READ:MISSPERF_COUNT_HW_CACHE_BPU:READ:ACCESSPERF_COUNT_HW_CACHE_BPU:READ:MISSPERF_COUNT_HW_CACHE_NODE:READ:ACCESSPERF_COUNT_HW_CACHE_NODE:READ:MISSPERF_COUNT_HW_CACHE_NODE:WRITE:ACCESSPERF_COUNT_HW_CACHE_NODE:WRITE:MISSPERF_COUNT_HW_CACHE_NODE:PREFETCH:ACCESSPERF_COUNT_HW_CACHE_NODE:PREFETCH:MISS%s (%s.%d): perf_find_pmu_type: cannot find PMU %s
%s/%s/perf_event_mux_interval_mswarning: mismatch attr struct size user=%d libpfm=%zu
%s (%s.%d): event %s with umasks with and without no_mods (%d) attribute, forcing no_mods
PERF[type=%x config=0x%lx config1=0x%lx excl=%d excl_user=%d excl_kernel=%d excl_hv=%d excl_host=%d excl_guest=%d period=%lu freq=%d precise=%d pinned=%d] %s
%s (%s.%d): sysfs_pmus[%d]=%s failed to get PMU type from sysfs
%s (%s.%d): sysf_pmus[%d]=%s type=%d
%s (%s.%d): No perf_name for %s, defaulting to TYPE_RAW
%s (%s.%d): cannot dup perf_name for %s
%s (%s.%d): cannot find perf_events PMU type for %s perf_name=%s using PERF_TYPE_RAW
perf_events raw event syntax: r[0-9a-fA-F]+%s (%s.%d): unsupported count=%d
%s (%s.%d): perf PMU %s, not supported by OS
%s (%s.%d): PMU %s perf type=%d
%s (%s.%d): perf_encoding: offcore=1 count=%d
%s (%s.%d): perf_encoding: frontend_retired=1 count=%d
%s (%s.%d): perf_encoding: ldlat count=%d
/sys/bus/event_source/devices/%s/type%s (%s.%d): amd64_get_perf_encoding: PMU type=%d
[0x%lx event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d%s (%s.%d): event does not support unit mask combination within a group
%s (%s.%d): raw umask is invalid
%s (%s.%d): added default for %s j=%d idx=%d
pmu: %s supported_plm not set
pmu: %s event%d: %s :: numasks but no umasks
pmu: %s event%d: %s :: numasks=0 but umasks defined
pmu: %s event%d: %s :: ngrp too big (max=%d)
pmu: %s event%d: %s :: more than one default unit mask with same code
pmu: %s event%d: %s, only one umask but no default
pmu: %s event%d: %s :: NCOMBO is unit mask only flag
pmu: %s event%d: %s :: umask %s and %s have overlapping code bits
pmu: %s events %s and %s have the same code 0x%x
Count core clock cycles whenever the clock signal on the specific core is running (not halted)Count the number of instructions at retirementThis is an alias from INSTRUCTION_RETIREDCount each request originating equiv the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESIThis is an alias for LLC_REFERENCESCount each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATEThis is an alias for LLC_MISSESCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.Count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware.Cycles micro-ops dispatched for executionNumber of micro-ops dispatched for executionNumber of of cycles in which no micro-ops is dispatched for executionCycles while stores are blocked due to store buffer drainNumber of segment register loadsStreaming SIMD Extensions (SSE) Prefetch instructions executedMemory accesses that missed the DTLBFloating point computational micro-ops executedCycles the divider is busy and all other execution units are idleCycles L2 address bus is in useCycles the L2 transfers data to the coreModified lines evicted from the L2 cacheL2 cacheable instruction fetch requestsCycles no L2 cache requests are pendingNumber of Enhanced Intel SpeedStep(R) Technology (EIST) transitionsCore cycles when core is not haltedL1 data cacheable locked readsAll references to the L1 data cacheL1 Data cacheable reads and writesCache lines allocated in the L1 data cacheModified cache lines allocated in the L1 data cacheModified cache lines evicted from the L1 data cacheTotal number of outstanding L1 data cache misses at any cycleCache line split from L1 data cacheStreaming SIMD Extensions (SSE) instructions missing all cache levelsLoad operations conflicting with a software prefetch to the same addressNumber of pending full cache line read transactions on the bus occurring in each cycleNumber of Bus Not Ready signals assertedBus cycles when data is sent on the busBus cycles when a LOCK signal is assertedBus cycles while processor receives dataExplicit writeback bus transactionsInstruction-fetch bus transactionsBurst (full cache-line) bus transactionsL1 data cache is snooped by other coreIO requests waiting in the bus queueCycles during which the instruction queue is fullCycles during which instruction fetches are stalledInstruction Length Decoder stall cycles due to a length changing prefixMispredicted branch instructions executedBranch instructions mispredicted at decodingConditional branch instructions executedMispredicted conditional branch instructions executedIndirect branch instructions executedMispredicted indirect branch instructions executedMispredicted RET instructions executedRET instructions executed mispredicted at decodingMispredicted CALL instructions executedIndirect CALL instructions executedBranch predicted taken with bubble IBranch predicted taken with bubble IIESP register content synchronizationSIMD micro-ops executed (excluding stores)SIMD saturated arithmetic micro-ops executedSIMD packed multiply micro-ops executedFused load+op or load+indirect branch retiredRetired mispredicted branch instructions (Precise_Event)Cycles during which interrupts are disabledCycles during which interrupts are pending and disabledRetired Streaming SIMD Extensions (SSE) packed-single instructionsRetired instructions that missed the ITLBRetired computational Streaming SIMD Extensions (SSE) packed-single instructionsRetired loads that miss the L1 data cacheTransitions from MMX (TM) Instructions to Floating Point InstructionsSaturated arithmetic instructions retiredCycles during which the ROB is fullUpward prefetches issued from the DPLDownward prefetches issued from the DPLCycles during which the RS is fullCycles during which the pipeline has exceeded load or store limit or waiting to commit all storesCycles stalled due to FPU control word writeCycles stalled due to branch mispredictionAny (ES/DS/FS/GS) segment renameAny (ES/DS/FS/GS) segment rename stallTransitions from Floating Point to MMX (TM) InstructionsRetired loads that miss the L1 data cache (Precise Event)L1 data cache line missed by retired loads (Precise Event)Retired loads that miss the L2 cache (Precise Event)L2 cache line missed by retired loads (Precise Event)Retired loads that miss the DTLB (Precise Event)Retired computational Streaming SIMD Extensions (SSE) scalar-single instructionsRetired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructionsRetired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsRetired Streaming SIMD Extensions (SSE) scalar-single instructionsRetired Streaming SIMD Extensions 2 (SSE2) packed-double instructionsRetired Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsRetired Streaming SIMD Extensions 2 (SSE2) vector integer instructionsRetired Streaming SIMD instructions (Precise Event)Retired branch instructions that were predicted not-takenRetired branch instructions that were mispredicted not-takenRetired branch instructions that were predicted takenRetired branch instructions that were mispredicted takenRetired taken branch instructionsExecution pipeline restart due to memory ordering conflict or memory disambiguation mispredictionFused store address + data retiredRetired instruction pairs fused into one micro-opRetired floating-point computational operations (Precise Event)Instructions retired (Precise Event)Instructions retired, which contain a loadInstructions retired, which contain a storeInstructions retired, with no load or store operationSIMD packed shift micro-ops executedSIMD unpack micro-ops executedSIMD packed logical micro-ops executedSIMD packed arithmetic micro-ops executedESP register automatic additionsL1 data cache is snooped for sharing by other coreL1 data cache is snooped for Invalidation by other coreL1 data cache prefetch requestsStreaming SIMD Extensions (SSE) Prefetch NTA instructions missing all cache levelsStreaming SIMD Extensions (SSE) PrefetchT0 instructions missing all cache levelsStreaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions missing all cache levelsCache line split loads from the L1 data cacheCache line split stores to the L1 data cacheM_STATE:E_STATE:S_STATE:I_STATEBus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratioBus cycles when core is active and the other is haltedDelayed bypass to FP operationDelayed bypass to SIMD operationDelayed bypass to load operationDuration of page-walks in core cyclesMemory disambiguation reset cyclesNumber of loads that were successfully disambiguatedAny memory access that missed the DTLBDTLB misses due to load operationsL0 DTLB misses due to load operationsDTLB misses due to store operationsStreaming SIMD Extensions (SSE) Prefetch NTA instructions executedStreaming SIMD Extensions (SSE) PrefetchT0 instructions executedStreaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executedStreaming SIMD Extensions (SSE) Weakly-ordered store instructions executedCycles while store is waiting for a preceding store to be globally observedA store is blocked due to a conflict with an external or internal snoopLoads blocked by a preceding store with unknown addressLoads blocked by a preceding store with unknown dataLoads that partially overlap an earlier store, or 4K equived with a previous storeLoads blocked until retirementLoads blocked by the L1 data cachePORT_0:PORT_1:PORT_2:PORT_3:PORT_4:PORT_5%s (%s.%d): added default %s for group %d j=%d idx=%d ucode=0x%lx
%s (%s.%d): two max_grpid, old=%d new=%d
%s (%s.%d): no default found for event %s unit mask group %d (max_grpid=%d)
%s (%s.%d): max_grpid=%d nattrs=%d k=%d umask=0x%lx
%s (%s.%d): exclusive unit mask group error
%s (%s.%d): event requires grpid %d
%s (%s.%d): umask %s does not support unit mask combination within group %d
%s (%s.%d): cannot override event with two different codes for %s
%s (%s.%d): raw umask is too wide max %d bits
%s (%s.%d): required grpid %d umask missing
%s (%s.%d): excl_grp_but_0=%d
%s (%s.%d): GRP_EXCL_BUT_0 but grpcounts[%d]=%d
%s (%s.%d): check: max_grpid=%d
%s (%s.%d): required modifiers missing: 0x%x
%s (%s.%d): um_thr=0x%lx fe_thr=%u thr_um=%u modhw=0x%x umodhw=0x%x
%s (%s.%d): passed ldlat= but not using ldlat umask
%s (%s.%d): missing ldlat= for umask, forcing to default %d cycles
%s (%s.%d): edge requires cmask >= 1
%s (%s.%d): event %s: umask from grp > %d
pmu: %s event%d: %s :: empty description
pmu: %s event%d: %s :: cntmsk=0
pmu: %s event%d: %s :: model too big (max=%d)
pmu: %s event%d: %s umask%d: %s :: modhw not subset of modmsk
pmu: %s event%d: umask%d: %s :: no description
pmu: %s event%d: umask%d: %s :: empty description
pmu: %s event%d: %s umask%d: %s :: invalid req_grpid %d (must be < %d)
pmu: %s event%d: %s umask%d: %s :: model too big (max=%d)
pmu: %s event%d: %s, pebs umasks but event pebs flag is not set
pmu: %s event%d: %s, pebs event flag but no umask has the pebs flag
pmu: %s event%d: %s, only one umask but no default set
pmu: %s event%d: %s grpid %d has 2 default umasks
pmu: %s event%d: %s :: NCOMBO is a umask only flag
%s (%s.%d): invalid event index %d
edge level (may require counter-mask >= 1)load latency threshold (cycles, [3-65535])monitor only inside transactional memory regiondo not count occurrences inside aborted transactional memory regionfrontend bubble latency threshold in cycles ([1-4095]%s (%s.%d): version=%d evt_msk=0x%x
count core clock cycles whenever the clock signal on the specific core is running (not halted)count the number of instructions at retirement. For instructions that consists of multiple micro-ops, this event counts the retirement of the last micro-op of the instructioncount reference clock cycles while the clock signal on the specific core is running. The reference clock operates at a fixed frequency, irrespective of core frequency changes due to performance state transitionscount each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetchcount each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetchcount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructioncount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareThis is an alias for INSTRUCTION_RETIREDLast level of cache referencesMispredicted branch instruction retiredRetired computational Streaming SIMD Extensions (SSE) instructionsRetired Streaming SIMD Extensions (SSE) instructionsHardware interrupts received (warning overcounts by 2x)Outstanding cacheable data read bus requests durationCycles the L2 cache data bus is busyFloating point computational micro-ops retiredRetired loads that hit the L2 cache (precise event)Retired loads that miss the L2 cache (precise event)Retired loads that miss the DTLB (precise event)Bus cycles when core is active and other is haltedL0 (micro-TLB) misses due to load operationsFloating point assists for executed instructionsFloating point assists for retired instructionsNon-CISC macro instructions decoded Retired mispredicted branch instructionsNumber of SIMD saturated arithmetic micro-ops executedNumber of SIMD saturated arithmetic micro-ops retiredRetired Streaming SIMD Extensions 2 (SSE2) vector instructionsRetired Streaming SIMD instructionsSIMD packed multiply micro-ops retiredSIMD packed shift micro-ops retiredSIMD packed micro-ops executedSIMD unpacked micro-ops executedSIMD unpacked micro-ops retiredSIMD packed logical micro-ops retiredSIMD packed arithmetic micro-ops retiredInstructions retired using generic counter (precise event)SIMD saturated arithmetic micro-ops retiredInstruction fetches, including uncacheacble fetchesCount all instructions fetches that miss the icache or produce memory requests. This includes uncacheache fetches. Any instruction fetch miss is counted only once and not once for every cycle it is outstanding%s (%s.%d): raw umask is 8-bit wide
[UNC_PERFEVTSEL=0x%lx event=0x%x umask=0x%x en=%d int=%d inv=%d edge=%d occ=%d cnt_msk=%d] %s
DRAM open commands issued for read or writeDRAM page close due to idle timer expirationDRAM Channel 0 precharge all commandsUncore cycles DRAM was throttled due to its temperature being above thermal throttling thresholdDRAM Channel 0 read CAS commandsDRAM Channel 0 refresh commandsDRAM Channel 0 write CAS commandsCycles GQ read tracker is full.Cycles GQ read tracker is busyLLC lines allocated in M stateLLC lines victimized in M stateQHL IOH Tracker conflict cyclesCycles QHL  Remote Tracker is fullCycles QHL Tracker is not emptyQHL FrcAckCnflts sent to local homeNumber of occurrences a request was put to sleepCycles QHL Tracker Allocate to Deallocate Read OccupancyQuickpath Home Logic local read requestsNumber of requests to QMC that bypass QHLCycles QMC busy with a read requestUNC_QMC_CRITICAL_PRIORITY_READSQMC critical priority read requestsQMC high priority read requestsCycles DRAM full with isochronous (ISOC) read requestsIMC isochronous (ISOC) Read OccupancyNumber of IMC DRAM channel retries (retries occur in RAS mode only)Link 0 snoop stalls due to no PPT entryCycles link 0 outbound header busyUNC_QPI_TX_STALLED_SINGLE_FLITCycles QPI outbound link stallsUncore cycles that the PCU records core temperature above thresholdUncore cycles that the PCU records that core is in power throttled state due to temperature being above thresholdNumber of system assertions of PROCHOT indicating the entire processor has exceeded the thermal limitUNC_THERMAL_THROTTLING_PROCHOTUncore cycles that the PCU records that core is in power throttled state due PROCHOT assertionsUncore cycles that a core is operating in turbo modeUNC_CYCLES_UNHALTED_L3_FLL_ENABLEUncore cycles where at least one core is unhalted and all L3 ways are enabledUNC_CYCLES_UNHALTED_L3_FLL_DISABLEUncore cycles where at least one core is unhalted and all L3 ways are disabledRemote home snoop response - LLC does not have cache lineRemote home snoop response - LLC has  cache line in S stateRemote home snoop response - LLC forwarding cache line in S state.Remote home snoop response - LLC has forwarded a modified cache lineRemote home conflict snoop responseRemote home snoop response - LLC has cache line in the M stateRemote home snoop response - LLC HITMLocal home snoop response - LLC does not have cache lineLocal home snoop response - LLC has  cache line in S stateLocal home snoop response - LLC forwarding cache line in S state.Local home snoop response - LLC has forwarded a modified cache lineLocal home conflict snoop responseLocal home snoop response - LLC has cache line in the M stateCycles QPI outbound link 0 HOME stalledCycles QPI outbound link 0 SNOOP stalledCycles QPI outbound link 0 NDR stalledCycles QPI outbound link 1 HOME stalledCycles QPI outbound link 1 SNOOP stalledCycles QPI outbound link 1 NDR stalledCycles QPI outbound link 0 single flit stalledCycles QPI outbound link 1 single flit stalledCycles QPI outbound link 0 DRS stalledCycles QPI outbound link 0 NCB stalledCycles QPI outbound link 0 NCS stalledCycles QPI outbound link 1 DRS stalledCycles QPI outbound link 1 NCB stalledCycles QPI outbound link 1 NCS stalledCycles QPI outbound link 0 multi flit stalledCycles QPI outbound link 1 multi flit stalledCycles link 1 outbound header busyLink 1 snoop stalls due to no PPT entryQMC channel 0 full cache line writesQMC channel 1 full cache line writesQMC channel 2 full cache line writesQMC channel 0 partial cache line writesQMC channel 1 partial cache line writesQMC channel 2 partial cache line writesQMC channel 0 priority updatesQMC channel 1 priority updatesQMC channel 2 priority updatesIMC channel 0 normal read request occupancyIMC channel 1 normal read request occupancyIMC channel 2 normal read request occupancyQMC channel 0 normal read requestsQMC channel 1 normal read requestsQMC channel 2 normal read requestsIMC channel 0 isochronous read request occupancyIMC channel 1 isochronous read request occupancyIMC channel 2 isochronous read request occupancyIMC isochronous read request occupancyCycles DRAM channel 0 full with isochronous read requestsCycles DRAM channel 1 full with isochronous read requestsCycles DRAM channel 2 full with isochronous read requestsCycles DRAM channel 0 full with isochronous write requestsCycles DRAM channel 1 full with isochronous write requestsCycles DRAM channel 2 full with isochronous write requestsQMC channel 0 high priority read requestsQMC channel 1 high priority read requestsQMC channel 2 high priority read requestsQMC channel 0 critical priority read requestsQMC channel 1 critical priority read requestsQMC channel 2 critical priority read requestsCycles QMC channel 0 busy with a read requestCycles QMC channel 1 busy with a read requestCycles QMC channel 2 busy with a read requestCycles QMC channel 0 busy with a write requestCycles QMC channel 1 busy with a write requestCycles QMC channel 2 busy with a write requestQuickpath Home Logic local write requestsQuickpath Home Logic remote read requestsQuickpath Home Logic IOH read requestsQuickpath Home Logic IOH write requestsQuickpath Home Logic remote write requestsCycles QHL IOH Tracker Allocate to Deallocate Read OccupancyCycles QHL Remote Tracker Allocate to Deallocate Read OccupancyCycles QHL Local Tracker Allocate to Deallocate Read OccupancyDue to IOH ordering (write after read) conflictsDue to remote socket ordering (write after read) conflictsDue to local socket ordering (write after read) conflictsDue to remote socket address conflictsDue to local socket address conflictsCycles QHL Remote Tracker is busyCycles QHL Local Tracker is busyCycles QHL Local Tracker is fullCycles QHL IOH Tracker is fullQHL Remote Tracker conflict cyclesQHL Local Tracker conflict cyclesNumber of LLC peer probe missesLLC lines victimized in E stateLLC lines victimized in S stateLLC lines victimized in I stateLLC lines victimized in F stateLLC lines allocated in E stateLLC lines allocated in S stateLLC lines allocated in F stateCycles GQ data sent to the QPI or QMCCycles GQ data is imported from Quickpath interfaceCycles GQ data is imported from Quickpath memory interfaceCycles GQ data is imported from LLCCycles GQ data is imported from Cores 0 and 2Cycles GQ data is imported from Cores 1 and 3Cycles GQ write tracker is busyCycles GQ peer probe tracker is busyCycles GQ write tracker is full.Cycles GQ peer probe tracker is full.GQ read tracker LLC miss to RTID acquiredGQ write tracker LLC miss to RTID acquiredGQ peer probe tracker requestsDRAM Channel 0 write CAS auto page close commandsDRAM Channel 1 write CAS commandsDRAM Channel 1 write CAS auto page close commandsDRAM Channel 2 write CAS commandsDRAM Channel 2 write CAS auto page close commandsDRAM Channel 1 refresh commandsDRAM Channel 2 refresh commandsDRAM Channel 0 read CAS auto page close commandsDRAM Channel 1 read CAS commandsDRAM Channel 1 read CAS auto page close commandsDRAM Channel 2 read CAS commandsDRAM Channel 2 read CAS auto page close commandsDRAM Channel 1 precharge all commandsDRAM Channel 2 precharge all commandsDRAM Channel 0 open commands issued for read or writeDRAM Channel 1 open commands issued for read or writeDRAM Channel 2 open commands issued for read or writeCycles DRAM full with normal read requestsCycles DRAM channel 0 full with normal read requestsCycles DRAM channel 1 full with normal read requestsCycles DRAM channel 2 full with normal read requestsCycles DRAM channel 0 full with normal write requestsCycles DRAM channel 1 full with normal write requestsCycles DRAM channel 2 full with normal write requestsminimal latency core cache hit. Request was satisfied by L1 data cachepending core cache HIT. Outstanding core cache miss to same cacheline address already underwaydata request satisfied by the L2L3 HIT. Local or remote home request that hit L3 in the uncore with no coherency actions required (snooping)L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where no modified copy was found (clean)L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where modified copies were found (HITM)L3 MISS. Local homed request that missed L3 and was serviced by forwarded data following a cross package snoop where no modified copy was found (remote home requests are not counted)L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to shared state)L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to shared state)L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to exclusive state)L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to exclusive state)This is an equiv for LLC_MISSESCounts arithmetic multiply and divide operationsInstruction queue forced BACLEARCounts the number of bogus branches.Branch prediction unit missed call or returnMispredicted branches executedCount Mispredicted Branch ActivityCycles when processor is not in halted stateFloating point computational micro-opsFloating Point to and from MMX transitionsInstruction Fetch unit victim cacheInstruction Length Decoder stallsInstructions written to instruction queue.Cycles instructions are written to the instruction queueCounts the number of ITLB flushesRetired instructions that missed the ITLB (Precise Event)L1D  cacheable loads. WARNING: event may overcount loadsL1D load lock accepted in fill bufferL1D_CACHE_PREFETCH_LOCK_FB_HITL1D prefetch load lock accepted in fill bufferOpportunistic hits in streamingLoad operations conflicting with software prefetchesLongest latency cache referenceMemory Disambiguation ActivityLoad instructions retired which hit offcoreCounts cycles the Offcore Request buffer or Super Queue is full.False dependencies due to partial address formingProgrammable interrupt controllerRegister allocation table stallsCounts number of segment register loads128 bit SIMD integer operations64 bit SIMD integer operationsCounts cycles the Offcore Request buffer or Super Queue is full and request(s) are outstanding.Super Queue Activity Related to L2 Cache AccessTwo micro-ops instructions decodedMicro-ops decoded by decoder 0Micro-ops unfusions due to FP exceptionsOffcore response 0 (must provide at least one request and one response umasks)Request: counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesRequest: counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFORequest: counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesRequest: counts the number of writeback (modified to exclusive) transactionsRequest: counts the number of data cacheline reads generated by L2 prefetchersRequest: counts the number of RFO requests generated by L2 prefetchersRequest: counts the number of code reads generated by L2 prefetchersRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockRequest: combination of PF_IFETCH | DMND_IFETCHRequest: combination of all requests umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:OTHERRequest: any data read/write requestDMND_DATA_RD:PF_DATA_RD:DMND_RFO:PF_RFORequest: any data read in requestRequest: combination of DMND_RFO | PF_RFOResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)Response: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)Response: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)Response: counts L3 Hit: local or remote home requests that hit a remote L3 cacheline in modified (HITM) stateResponse: counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)Response: counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAMResponse: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAMResponse: Non-DRAM requests that were serviced by IOHResponse: requests serviced by any source but IOHUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAMResponse: requests serviced by local or remote DRAMResponse: requests that missed in L3REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAMResponse: requests hit local core or uncore caches or local DRAMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:LOCAL_DRAMResponse: requests that miss L3 and hit remote caches or DRAMREMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAMResponse: combination of all response umasksUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAM:NON_DRAMRetirement slots used (Precise Event)Cycles Uops are being retired (Precise Event)Cycles No Uops retired (Precise Event)Macro-fused Uops retired (Precise Event)Uops executed on port 2 on any thread (core count only)Uops executed on port 3 on any thread (core count only)Uops executed on port 4 on any thread (core count only)Uops issued on ports 0, 1 or 5Uops issued on ports 2, 3 or 4 on any thread (core count only)Cycles no Uops issued on ports 0, 1 or 5Stack pointer instructions decodedUops decoded by Microcode SequencerCycles in which at least one uop is decoded by Microcode SequencerLoads delayed with at-Retirement block codeCacheable loads delayed with L1D block codeLoads delayed due to a store blocked for unknown dataLoads delayed due to a store blocked for an unknown addressSIMD Packed-Double Uops retired (Precise Event)SIMD Packed-Single Uops retired (Precise Event)SIMD Scalar-Double Uops retired (Precise Event)SIMD Scalar-Single Uops retired (Precise Event)SIMD Vector Integer Uops retired (Precise Event)Streaming SIMD L1D NTA prefetch missCounts the number of L2 secondary misses that hit the Super QueueCounts the number of L2 secondary misses during the Super Queue filling L2Counts number of Super Queue LRU hints sent to L3Counts the number of SQ L2 fills dropped due to L2 busySuper Queue lock splits across a cache lineThread responded HITE to snoopThread responded HITM to snoopSIMD integer 64 bit pack operationsSIMD integer 64 bit arithmetic operationsSIMD integer 64 bit logical operationsSIMD integer 64 bit packed multiply operationsSIMD integer 64 bit shift operationsSIMD integer 64 bit shuffle/move operationsSIMD integer 64 bit unpack operations128 bit SIMD integer pack operations128 bit SIMD integer arithmetic operations128 bit SIMD integer logical operations128 bit SIMD integer multiply operations128 bit SIMD integer shift operations128 bit SIMD integer shuffle/move operations128 bit SIMD integer unpack operationsFPU control word write stall cyclesReservation Station full stall cyclesOther Resource related stall cyclesCounts number of offcore demand code read requests. Does not count L2 prefetch requests.Offcore demand data read requestsOffcore L1 data cache writebacksCounts number of offcore uncached memory requestsLoad instructions retired that HIT modified data in sibling core (Precise Event)Load instructions retired remote cache HIT data source (Precise Event)Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)Load instructions retired where the memory reference missed L3 and data source is unknown (Model 46 only, Precise Event)Load instructions retired where the memory reference missed L1, L2, L3 caches and to perform I/O (Model 46 only, Precise Event)Retired stores that miss the DTLB (Precise Event)Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)Retired loads that hit the L1 data cache (Precise Event)Retired loads that hit the L2 cache (Precise Event)Retired loads that miss the L3 cache (Precise Event)Retired loads that hit valid versions in the L3 cache (Precise Event)This is an alias for L3_UNSHARED_HITRetired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)Memory instructions retired above programmed clocks, minimum threshold value is 3, (Precise Event and ldlat required)Instructions retired which contains a load (Precise Event)Instructions retired which contains a store (Precise Event)Counts memory disambiguation reset cyclesCounts the number of times the memory disambiguation watchdog kicked inCounts the cycles that the memory disambiguation watchdog is activeMacro-fused instructions decodedExecution pipeline restart due to Memory ordering conflictsCounts the number of macro-fusion assistsCycles when uops were delivered by the LSDCycles no uops were delivered by the LSDLoads dispatched that bypass the MOBLoads dispatched from stage 305L2 demand lock RFOs in E stateL2 demand lock RFOs in I state (misses)L2 demand lock RFOs in S stateAll demand L2 lock RFOs that hit the cacheL2 demand lock RFOs in M stateAll L2 demand store RFOs that hit the cacheL2 demand store RFOs in I state (misses)L2 demand store RFOs in the E state (exclusive)L2 demand store RFOs in M stateL2 demand store RFOs in S stateL2 instruction fetch transactionsL1D writeback to L2 transactionsL2 writeback to LLC transactionsL2 lines evicted by a demand requestL2 modified lines evicted by a demand requestL2 lines evicted by a prefetch requestL2 modified lines evicted by a prefetch requestL2 lines allocated in the E stateL2 lines allocated in the S stateCount L2 HW prefetcher detector hitsCount L2 HW prefetcher allocationsCount L2 HW data prefetcher triggeredCount L2 HW code prefetcher triggeredCount L2 HW DCA prefetcher triggeredCount L2 HW prefetcher kick startedL2 data demand loads in E stateL2 data demand loads in I state (misses)L2 data demand loads in M stateL2 data demand loads in S stateL2 data prefetches in the I state (misses)L2 data prefetches in the S stateL1I instruction fetch stall cyclesL1 writebacks to L2 in E stateL1 writebacks to L2 in I state (misses)L1 writebacks to L2 in M stateL1 writebacks to L2 in S stateL1D hardware prefetch requestsL1D hardware prefetch requests triggeredL1 data cache stores in E stateL1 data cache store in the I stateL1 data cache stores in M stateL1 data cache stores in S stateL1 data cache store in all statesL1 data cache load locks in E stateL1 data cache load locks in M stateL1 data cache load locks in S stateL1 data cache read in I state (misses)L1 data cacheable reads and writesL1D cache lines replaced in M stateL1D cache lines allocated in the M stateL1D snoop eviction of cache lines in M stateInstructions Retired (Precise Event)Retired floating-point operations (Precise Event)Instructions that must be decoded by decoder 0Any Instruction Length Decoder stall cyclesInstruction Queue full stall cyclesLength Change Prefix stall cyclesStall cycles due to BPU MRU bypassInstruction Fetche unit victim cache fullL1 Instruction cache evictionsAll Floating Point to and from MMX transitionsTransitions from MMX to Floating Point instructionsTransitions from Floating Point to MMX instructionsComputational floating-point operations executedFloating point assists (Precise Event)Floating point assists for invalid input value (Precise Event)Floating point assists for invalid output value (Precise Event)Extended Page Directory Entry missExtended Page Directory Pointer missExtended Page Directory Pointer hitDTLB first level misses but second level hitNumber of DTLB cache misses where the low part of the linear to physical address translation was missedNumber of DTLB misses where the high part of the linear to physical address translation was missedCounts number of completed large page walks due to misses in the STLBDTLB load miss caused by low part of addressDTLB load miss page walks completeNumber of DTLB cache load misses where the high part of the linear to physical address translation was missedCounts number of completed large page walks due to load miss in the STLBCycles when thread is not halted (programmable counter)Reference base clock (133 Mhz) cycles when thread is not haltedTotal number of elapsed cycles. Does not work when C-state enabledCounts mispredicted direct and indirect near unconditional retired callsMispredicted conditional branches executedMispredicted unconditional branches executedMispredicted non call branches executedMispredicted indirect call branches executedMispredicted indirect non call branches executedMispredicted call branches executedMispredicted return branches executedMispredicted taken branches executedRetired branch instructions (Precise Event)Retired conditional branch instructions (Precise Event)Retired near call instructions (Precise Event)Unconditional branches executedUnconditional call branches executedIndirect call branches executedIndirect non call branches executedAll non call branches executedIndirect return branches executedEarly Branch Prediction Unit clearsLate Branch Prediction Unit clearsCount any Branch Prediction Unit clearsBACLEAR asserted with bad target addressBACLEAR asserted, regardless of causeCounts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.Counts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.Counts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD.Intel Westmere (single-socket)Count core clock cycles whenever the clock signal on the specific core is running (not halted).Count the number of instructions at retirement.Count each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch (Alias for L3_LAT_CACHE:REFERENCE).This is an alias for L3_LAT_CACHE:REFERENCECount each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch (Alias for L3_LAT_CACHE:MISS)This is an alias for L3_LAT_CACHE:MISSL1D cacheable load lock speculated or retired accepted into the fill bufferMispredicted retired branches (Precise Event)SIMD micro-ops retired (Precise Event)Offcore requests blocked due to Super Queue fullSIMD 64-bit integer operationsBranch address calculator clearsMemory instructions retired (Precise Event)BACLEAR forced by Instruction queueNumber of loops that cannot stream from the instruction queue.X87 Floating point assists (Precise Event)Count the number of instructions decoded that are macros-fused but not necessarily executed or retiredFalse dependencies due to partial address aliasingLoad instructions retired (Precise Event)Memory loads retired (Precise Event)Count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareCounts unfusion events due to floating point exception to a fused uopOffcore response 1 (must provide at least one request and one response umasks)LOCAL_DRAM_AND_REMOTE_CACHE_HITResponse: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM or a remote cacheResponse: counts L3 Miss: remote home requests that missed the L3 cacheUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:OTHER_LLC_MISS:REMOTE_DRAM:LOCAL_DRAM_AND_REMOTE_CACHE_HITREMOTE_CACHE_HITM:REMOTE_DRAM:OTHER_LLC_MISS:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:NON_DRAMResponse: any local (core and socket) cachesUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:REMOTE_DRAM:OTHER_LLC_MISS:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:NON_DRAMFLAGS:REGISTERS:ROB_READ_PORT:SCOREBOARDL1D cache lines replaced in M state Retired loads that miss the LLC cache (Precise Event)Retired loads that hit valid versions in the LLC cache (Precise Event)Outstanding snoop code requestsCycles snoop code requests queue not emptyOutstanding snoop data requestsCycles snoop data requests queue not emptyOutstanding snoop invalidate requestsCycles snoop invalidate requests queue not emptyLoad instructions retired local dram and remote cache HIT data sources (Precise Event)Load instructions retired IO (Precise Event)Retired loads that hit remote socket in modified state (Precise Event)Load instructions retired other LLC miss (Precise Event)Load instructions retired unknown LLC miss (Precise Event)Retired loads with a data source of local DRAM or locally homed remote cache HITM (Precise Event)Retired loads instruction that hit modified data in sibling core (Precise Event)Retired loads instruction that hit remote cache hit data source (Precise Event)Retired loads instruction remote DRAM and remote home-remote cache HITM (Precise Event)Counts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Count may be incorrect when HT is onCounts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Count may be incorrect when HT is onCounts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect when HT is onOutstanding offcore demand code readsOutstanding offcore demand data readsOutstanding offcore demand RFOsNumber of cycles with offcore reads busyNumber of cycles with offcore demand data reads busyNumber of cycles with offcore code reads busyNumber of cycles with offcore rfo busyAll X87 Floating point assists (Precise Event)X87 Floating point assists for invalid input value (Precise Event)X87 Floating point assists for invalid output value (Precise Event)Super Queue LRU hints sent to LLCNumber of completed large page walks due to misses in the STLBITLB misses hitting second level TLBCounts the number of micro-ops delivered by LSDCycles is which at least one micro-op delivered by LSDCycles is which no micro-op is delivered by LSDExecution pipeline restart due to Memory ordering conflicts Cycles machine clear is assertedStore referenced with misaligned addressLoads that partially overlap an earlier storeOffcore demand code read requestsNumber of loads dispatched from the Reservation Station (RS) that bypass the Memory Order BufferNumber of delayed RS dispatches at the stage latchNumber of loads dispatched from Reservation Station (RS)Cycles uops issued on either threads (core count)Cycles no uops issued on any threads (core count)DTLB miss caused by low part of addressDTLB load miss page walk cyclesDTLB load miss large page walk cyclesRetired MMX instructions (Precise Event)Uops executed on port 0 (integer arithmetic, SIMD and FP add uops)Uops executed on port 1 (integer arithmetic, SIMD, integer shift, FP multiply, FP divide uops)Uops executed on port 2 on any thread (load uops) (core count only)Uops executed on port 3 on any thread (store uops) (core count only)Uops executed on port 4 on any thread (handle store values for stores on port 3) (core count only)Cycles in which uops are executed only on port0-4 on any thread (core count only)Cycles in which uops are executed on any port any thread (core count only)Cycles in which no uops are executed on any port any thread (core count only)Cycles in which no uops are executed on any port0-4 on any thread (core count only)Number of transitions from stalled to uops to execute on any port any thread (core count only)Number of transitions from stalled to uops to execute on ports 0-4 on any thread (core count only)CORE_STALL_CYCLES_NO_PORT5:e:t:i:c=1Extended Page Table walk cyclesMispredicted retired branch instructions (Precise Event)Mispredicted near retired calls (Precise Event)Mispredicted conditional branches retired (Precise Event)Cycles Uops are not retiring (Precise Event)Total cycles using precise uop retired event (Precise Event)Alias for TOTAL_CYCLES (Precise Event)Counts the number of uops decoded by the Microcode Sequencer (MS). The MS delivers uops when the instruction is more than 4 uops long or a microcode assist is occurring.Number of executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another pageCounts arithmetic multiply operationsCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructionUnhalted core cycles at a specific ring levelNumber of DSB to MITE switchesCounts number of floating point eventsNumber of instructions at retirementWriteback requests from L1D to L2Alias for LAST_LEVEL_CACHE_MISSESAlias for LAST_LEVEL_CACHE_REFERENCESLoad dispatches that hit fill bufferCore-originated cacheable demand requests to L3L3 hit loads uops retired (deprecated use MEM_LOAD_UOPS_LLC_HIT_RETIRED)Loads and some non simd split loads uops retiredLoads and some non simd split loads uops retired (deprecated use MEM_LOAD_UOPS_MISC_RETIRED)Memory loads uops retired (deprecated use MEM_LOAD_UOPS_RETIRED)Memory uops retired (deprecated use MEM_UOPS_RETIRED)Partial Register Allocation Table stallsCounts 256-bit packed floating point instructionsUops dispatch to specific portsMEM_LOAD_UOPS_LLC_MISS_RETIREDLoad uops retired which miss the L3 cacheOffcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)Load uops that miss in the L3 and hit local DRAMLoad uops that miss in the L3 and hit remote DRAMCounts total number of uops executed from any thread per cycleCounts total number of uops executed per thread each cycleNumber of cycles with no uops executedCycles where at least 1 uop was executed per threadCycles where at least 2 uops were executed per threadCycles where at least 3 uops were executed per threadCycles where at least 4 uops were executed per threadCycles where at least 1 uop was executed from any threadCycles where at least 2 uops were executed from any threadCycles where at least 3 uops were executed from any threadCycles where at least 4 uops were executed from any threadCycles where no uop is executed on any threadNumber of page walks with a LLC missNumber of uops delivered by the Loop Stream Detector (LSD)Cycles with uops delivered by the LSD but which did not come from decoderCycles with 4 uops delivered by the LSD but which did not come from decoderCycles for an extended page table walkCycles with pending L2 miss loadsCycles with pending L1D load cache missesExecution stalls due to L2 pending loadsExecution stalls due to L1D pending loadsCounts the number of times the front end is re-steered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front endRequest: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesRequest: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetchesRequest: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesRequest: number of writebacks (modified to exclusive) transactionsRequest: number of data cacheline reads generated by L2 prefetchersRequest: number of RFO requests generated by L2 prefetchersRequest: number of code reads generated by L2 prefetchersRequest: number of L3 prefetcher requests to L2 for loadsRequest: number of RFO requests generated by L2 prefetcherRequest: number of L2 prefetcher requests to L3 for instruction fetchesRequest: number bus lock and split lock requestsRequest: number of streaming store requestsRequest: combination of PF_IFETCH | DMND_IFETCH | PF_LLC_IFETCHPF_IFETCH:DMND_IFETCH:PF_LLC_IFETCHRequest: combination of all request umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHERRequest: combination of DMND_DATA | PF_DATA_RD | PF_LLC_DATA_RDDMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RDRequest: combination of DMND_RFO | PF_RFO | PF_LLC_RFOResponse: count any response typeSupplier: counts number of times supplier information is not availableSupplier: counts L3 hits in M-state (initial lookup)Supplier: counts L3 hits in E-stateSupplier: counts L3 hits in S-stateSupplier: counts L3 hits in F-stateSupplier: counts L3 misses to local DRAMSupplier: counts L3 misses to remote DRAMSupplier: counts L3 misses to local or remote DRAMLLC_MISS_LOCAL:LLC_MISS_REMOTESupplier: counts L3 hits in any state (M, E, S, F)LLC_HITM:LLC_HITE:LLC_HITS:LLC_HITFSnoop: counts number of times no snoop-related information is availableSnoop: counts the number of times no snoop was needed to satisfy the requestSnoop: counts number of times a snoop was needed and it missed all snooped cachesSnoop: counts number of times a snoop was needed and it hit in at leas one snooped cacheSnoop: counts number of times a snoop was needed and data was forwarded from a remote socketSnoop: counts number of times a snoop was needed and it hitM-ed in local or remote cacheSnoop:  counts number of times target was a non-DRAM system address. This includes MMIO transactionsSNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAMAll uops that actually retired (Precise Event)Number of retirement slots used (Precise Event)Cycles no executable uop retired (Precise Event)Number of uops issued by the RAT to the Reservation Station (RS)Cycles no uops issued on this core (by any thread)Cycles no uops issued by this threadCycles which a Uop is dispatched on port 0Cycles which a Uop is dispatched on port 1Cycles in which a load uop is dispatched on port 2Cycles in which a store uop is dispatched on port 2Cycles in which a uop is dispatched on port 2Cycles in which a uop is dispatched on port 3Cycles which a uop is dispatched on port 4Cycles which a Uop is dispatched on port 5Cycles in which a uop is dispatched on port 0 for any threadCycles in which a uop is dispatched on port 1 for any threadCycles in which a uop is dispatched on port 2 for any threadCycles in which a uop is dispatched on port 3 for any threadCycles in which a uop is dispatched on port 4 for any threadCycles in which a uop is dispatched on port 5 for any threadNumber of DTLB flushes of thread-specific entriesCounts 256-bit packed single-precisionCounts 256-bit packed double-precisionCycles the RS is empty for this threadCounts number of time the Reservation Station (RS) goes from empty to non-emptyCount each time an new LBR record is saved by HWCycles stalled due to free list emptyCycles stalls due to control structures full for physical registersCycles Allocator is stalled due Branch Order BufferCycles stalled due to out of order resources fullCycles stalled due to Resource Related reasonCycles stalled due to lack of load buffersCycles stalled due to no eligible RS entry availableCycles stalled due to no store buffers available (not including draining from sync)Cycles stalled due to re-order buffer fullCycles stalled due to writing the FPU control wordCycles stalled due to the MXCSR register ranme occurring too close to a previous MXCSR renameCycles stalled due to LB, SB or RS being completely in useResource stalls due to load or store buffers all being in useResource stalls due to Rob being full, FCSW, MXCSR and OTHERNumber of flags-merge uops in flight in each cycleCycles in which flags-merge uops in flightNumber of Multiply packed/scalar single precision uops allocatedNumber of cycles with at least one slow LEA uop allocatedNumber of instructions that experienced an ITLB missNumber of transitions from AVX-256 to legacy SSE when penalty applicableNumber of transitions from legacy SSE to AVX-256 when penalty applicableNumber of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operationsCycles with cacheable data read transactions in the superQCycles with demand code reads transactions in the superQCycles with demand data read transactions in the superQCacheable data read transactions in the superQ every cycleCode read transactions in the superQ every cycleDemand data read transactions in the superQ every cycleCycles with at lesat 6 offcore outstanding demand data read requests in the uncore queueOutstanding RFO (store) transactions in the superQ every cycleCycles with outstanding RFO (store) transactions in the superQOffcore requests buffer cannot take more entries for this thread coreDemand and prefetch read requests sent to uncoreOffcore code read requests, including cacheable and un-cacheablesDemand Data Read requests sent to uncoreOffcore Demand RFOs, includes regular RFO, Locks, ItoMSpeculative cache-line split load uops dispatched to the L1DSpeculative cache-line split Store-address uops dispatched to L1DAny retired loads (Precise Event)Any retired stores (Precise Event)Locked retired loads (Precise Event)Locked retired stores (Precise Event)Retired loads causing cacheline splits (Precise Event)Retired stores causing cacheline splits (Precise Event)STLB misses dues to retired loads (Precise Event)STLB misses dues to retired stores (Precise Event)Memory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)Capture where stores occur, must use with PEBS (Precise Event required)A load missed L1D but hit the Fill Buffer (Precise Event)Load hit in nearest-level (L1D) cache (Precise Event)Load hit in mid-level (L2) cache (Precise Event)Load hit in last-level (L3) cache with no snoop needed (Precise Event)Retired load uops which data sources were data missed LLC (excluding unknown data source)Counts load driven L3 misses and some non simd split loads (Precise Event)Load LLC Hit and a cross-core Snoop hits in on-pkg core cache (Precise Event)Load had HitM Response from a core on same socket (shared LLC) (Precise Event)Load LLC Hit and a cross-core Snoop missed in on-pkg core cache (Precise Event)The number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0Number of Memory Ordering Machine Clears detectedNumber of machine clears (nukes) of any typeCore-originated cacheable demand requests missed L3Core-originated cacheable demand requests that refer to L3Non sw-prefetch load dispatches that hit the fill buffer allocated for HW prefetchNon sw-prefetch load dispatches that hit the fill buffer allocated for SW prefetchFalse dependencies in MOB due to partial compare on addressNumber of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this typeBlocked loads due to store buffer blocks with unknown dataLoads blocked by overlapping with store buffer that cannot be forwardedNumber of split loads blocked due to resource not availableNumber of cases where any load is blocked but has not DCU missTransactions accessing MLC pipeL2 cache accesses when fetching instructionsL1D writebacks that access L2 cacheDemand Data Read* requests that access L2 cacheL2 fill requests that access L2 cacheL2 writebacks that access L2 cacheL2 or L3 HW prefetches that access L2 cache (including rejects)RFO requests that access L2 cacheRFOs that hit cache lines in E stateRFOs that miss cache (I state)RFOs that hit cache lines in M stateRFOs that access cache lines in any stateAny ifetch request to L2 cacheL2 cache hits when fetching instructionsL2 cache misses when fetching instructionsDemand  data read requests to L2 cacheDemand data read requests that hit L2Any L2 HW prefetch request to L2 cacheRequests from the L2 hardware prefetchers that hit L2 cacheRequests from the L2 hardware prefetchers that miss L2 cacheRFO requests that hit L2 cacheRFO requests that miss L2 cacheL2 clean line evicted by a demandL2 dirty line evicted by a demandL2 clean line evicted by a prefetchL2 dirty line evicted by an MLC PrefetchAny L2 dirty line evicted (does not cover rejects)L2 cache lines filling (counting does not cover rejects)L2 cache lines in E state (counting does not cover rejects)L2 cache lines in I state (counting does not cover rejects)L2 cache lines in S state (counting does not cover rejects)Non rejected writebacks from L1D to L2 cache lines in E stateNon rejected writebacks from L1D to L2 cache lines in M stateNon rejected writebacks from L1D to L2 cache lines in S stateNumber of modified lines evicted from L1 and missing L2 (non-rejected WB from DCU)Occurrences of L1D_PEND_MISS going activeNumber of L1D load misses outstanding every cycleCycles with L1D load misses outstandingCycles with L1D load misses outstanding from any threadNumber of cycles a demand request was blocked due to Fill Buffer (FB) unavailabilityNumber of dispatched loads cancelled due to L1D bank conflicts with other load portsCycles when dispatched loads are cancelled due to L1D bank conflicts with other load portsNumber of allocations of L1D cache lines in modified (M) stateNumber of cache lines in M-state evicted of L1D due to snoop HITM or dirty line replacementNumber of modified lines evicted from L1D due to replacementNumber of cache lines brought into the L1D cacheNumber of ITLB flushes, includes 4k/2M/4M pagesCycles RAT external stall is sent to IDQ for this threadCycles waiting to be recovered after Machine Clears due to all other cases except JEClearNumber of times need to wait after Machine Clears due to all other cases except JEClearCycles during which the allocator was stalled due to recovery from earlier clear event for any thread (e.g. misprediction or memory nuke)Number of instructions retiredPrecise instruction retired event to reduce effect of PEBS shadow IP distribution (Precise Event)Number of instructions written to IQ every cycleStall caused by changing prefix length of the instructionNumber of non-delivered uops to RAT (use cmask to qualify further)Cycles per thread when 4 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalledCycles per thread when 1 or more uops are delivered to the Resource Allocation Table (RAT) by the front endCycles per thread when 3 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalledCycles with less than 2 uops delivered by the front endCycles with less than 3 uops delivered by the front endCycles Front-End (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling FENumber of uops delivered to IDQ from MITE pathNumber of uops delivered to IDQ from DSB pathNumber of uops delivered to IDQ when MS busy by DSBNumber of uops delivered to IDQ when MS busy by MITENumber of uops were delivered to IDQ from MS by either DSB or MITECycles where uops are delivered to IDQ from MITE (MITE active)Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITECycles where uops are delivered to IDQ from DSB (DSB active)Cycles where uops delivered to IDQ when MS busy by DSBCycles where uops delivered to IDQ when MS busy by MITECycles where uops delivered to IDQ from MS by either BSD or MITENumber of uops deliver from either DSB pathsCycles MITE/MS deliver anythingCycles Decode Stream Buffer (DSB) is delivering 4 UopsNumber of uops delivered from either MITE pathsCycles DSB/MS deliver anythingCycles MITE is delivering 4 UopsNumber of uops delivered to IDQ from any pathOccurrences of DSB MS going activeNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accessesNumber of Instruction Cache, Streaming Buffer and Victim Cache Reads. Includes cacheable and uncacheable accesses and uncacheable fetchesHardware prefetch requests that misses the L1D cache. A request is counted each time it accesses the cache and misses it, including if a block is applicable or if it hits the full buffer, for example. This accounts for both L1 streamer and IP-based Hw prefetchersNumber of SSE double precision FP packed uops executedNumber of SSE single precision FP scalar uops executedNumber of SSE single precision FP packed uops executedNumber of SSE double precision FP scalar uops executedCycles with any input/output SSE or FP assistsNumber of SIMD FP assists due to input valuesNumber of SIMD FP assists due to output valuesNumber of X87 assists due to input valueNumber of X87 assists due to output valueCycles with any input and output SSE or FP assistMiss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)First level miss but second level hit; no page walk. Only relevant if multiple levelsMiss in all TLB levels that causes a page walk that completes of any page size (4K/2M/4M/1G)Cycles PMH is busy with this walkDemand load miss in all TLB levels which causes an page walk of any page sizeNumber of DTLB lookups for loads which missed first level DTLB but hit second level DTLB (STLB); No page walk.Demand load miss in all TLB levels which causes a page walk that completes for any page sizeCycles PMH is busy with a walkNumber of times a valid DSB fill has been cancelled for any reasonDSB Fill encountered > 3 DSB linesNumber of times a valid DSB fill has been cancelled not because of exceeding way limitCycles SB to MITE switches caused delayCycles when the core is unhalted (count at 100 Mhz)Count Xclk pulses (100Mhz) when the core is unhaltedCount Xclk pulses (100Mhz) when the at least one thread on the physical core is unhaltedCycles when thread is not haltedCounts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is haltedUnhalted core cycles the thread was in ring 0Transitions from rings 1, 2, or 3 to ring 0Unhalted core cycles the thread was in rings 1, 2, or 3Cycles in which the L1D and L2 are locked, due to a UC lock or split lockCycles in which the L1D is lockedAll mispredicted macro branches (Precise Event)All mispredicted macro conditional branch instructions (Precise Event)All macro direct and indirect near calls (Precise Event)Number of branch instructions retired that were mispredicted and not-taken (Precise Event)Number of branch instructions retired that were mispredicted and taken (Precise Event)All non-taken mispredicted macro conditional branch instructionsAll taken mispredicted macro conditional branch instructionsTAKEN_INDIRECT_JUMP_NON_CALL_RETAll taken mispredicted indirect branches that are not calls nor returnsAll taken mispredicted indirect branches that have a return mnemonicAll taken mispredicted non-indirect callsAll taken mispredicted indirect calls, including both register and memory indirectAll mispredicted macro conditional branch instructionsAll mispredicted non-indirect callsANY_INDIRECT_JUMP_NON_CALL_RETAll mispredicted indirect branches that are not calls nor returnsAll mispredicted branch instructionsAll taken and not taken macro branches including far branches (Precise Event)All taken and not taken macro conditional branch instructions (Precise Event)Number of far branch instructions retired (Precise Event)All macro direct and indirect near calls, does not count far calls (Precise Event)Number of near ret instructions retired (Precise Event)Number of near branch taken instructions retired (Precise Event)All not taken macro branch instructions retired (Precise Event)All macro conditional non-taken branch instructionsAll macro conditional taken branch instructionsAll macro unconditional taken branch instructions, excluding calls and indirectsAll taken indirect branches that are not calls nor returnsAll taken indirect branches that have a return mnemonicAll taken indirect calls, including both register and memory indirectAll near executed branches instructions (not necessarily retired)All macro conditional branch instructionsAll indirect branches that are not calls nor returnsSpeculative and retired macro-unconditional branches excluding calls and indirectsSpeculative and retired indirect return branchesCycles that the divider is active, includes integer and floating pointNumber of cycles the divider is activated, includes integer and floating pointThis event counts executed load operationsIntel Sandy Bridge C-box3 uncoreIntel Sandy Bridge C-box2 uncoreIntel Sandy Bridge C-box1 uncoreIntel Sandy Bridge C-box0 uncoreSnoop responses (must provide a snoop type and filter)Number of LLC lookup requests for a line in modified stateNumber of LLC lookup requests for a line in exclusive stateNumber of LLC lookup requests for a line in shared stateNumber of LLC lookup requests for a line in invalid stateNumber of LLC lookup requests for a lineFilter on processor core initiated cacheable read requestsFilter on processor core initiated cacheable write requestsFilter on external snoop requestsFilter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requestsNumber of snoop invalidates of a non-modified lineNumber of snoop hits of a non-modified lineNumber of snoop hits of a modified lineNumber of snoop invalidates of a modified lineFilter on cross-core snoops initiated by this Cbox due to external snoop requestFilter on cross-core snoops initiated by this Cbox due to processor core memory requestFilter on cross-core snoops initiated by this Cbox due to LLC evictionLoad uops retired that missed the LLCNumber of split locks in the super queue (SQ)Number of cycles the offcore requests buffer is fullCycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)Number of occurrences waiting for Machine ClearsNumber of SSE or AVX-128 double precision FP packed uops executedNumber of SSE or AVX-128 single precision FP scalar uops executedNumber of SSE or AVX-128 single precision FP packed uops executedNumber of SSE or AVX-128 double precision FP scalar uops executedCycles with pending memory loadsExecution stalls due to memory loadsNumber of flags-merge uops allocated. Such uops adds delayNumber of slow LEA or similar uops allocatedNumber of multiply packed/scalar single precision uops allocatedCycles in which a uop is dispatched on port 0Cycles in which a uop is dispatched on port 1Cycles in which a uop is dispatched on port 4Cycles in which a uop is dispatched on port 5Number of load operations that missed L1TLB but hit L2TLBNumber of assists associated with 256-bit AVX storesNumber of times the microcode assist is invoked by hardware upon uop writebackLoad miss in nearest-level (L1D) cache (Precise Event)Load misses in mid-level (L2) cache (Precise Event)Load miss in last-level (L3) cache (Precise Event)Number of retired load uops that missed L3 but were service by local RAM. Does not count hardware prefetches (Precise Event)Number of retired load uops that missed L3 but were service by remote RAM, snoop not needed, snoop miss, snoop hit data not forwarded (Precise Event)Number of retired load uops whose data sources was remote HITM (Precise Event)Load uops that miss in the L3 whose data source was forwarded from a remote cache (Precise Event)Number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useTransactions accessing the L2 pipeL1D writebacks that access the L2 cacheDemand Data Read requests that access the L2 cacheL2 fill requests that access the L2 cacheL2 writebacks that access the L2 cacheL2 or L3 HW prefetches that access the L2 cache (including rejects)RFO requests that access the L2 cacheStore RFO requests that hit L2 cacheNot rejected writebacks that missed LLCNot rejected writebacks from L1D to L2 cache lines in any stateCycles with L1D load misses outstanding from any thread on the physical coreNumber of integer Move Elimination candidate uops that were not eliminatedNumber of SIMD Move Elimination candidate uops that were not eliminatedNumber of integer Move Elimination candidate uops that were eliminatedNumber of SIMD Move Elimination candidate uops that were eliminatedNumber of uops delivered from either DSB pathsCycles MITE/MS delivered anythingCycles MITE/MS delivered 4 uopsCycles DSB/MS delivered anythingCycles MITE is  delivering 4 uopsNumber of cycles wher a code-fetch stalled due to L1 instruction cache miss or iTLB missNumber of completed page walks in ITLB due to STLB load misses for large pagesDemand load miss in all TLB levels which causes a page walk of any page sizeCycles PMH is busy with a walk due to demand loadsNumber of large page walks completed for demand loadsNumber of DSB to MITE switch true penalty cyclesIntel Ivy Bridge C-box3 uncoreIntel Ivy Bridge C-box2 uncoreIntel Ivy Bridge C-box1 uncoreIntel Ivy Bridge C-box0 uncoreBranch instructions retired (Precise Event)Number of instructions retired (Precise Event)Demand Data Read requests to L2L3 hit load uops retired (Precise Event)Load uops retired that missed the L3 (Precise Event)Retired load uops (Precise Event)Memory transactions retired (Precise Event)Memory uops retired (Precise Event)Cycles Allocation is stalled due to Resource Related reasonRestricted Transaction Memory execution (Precise Event)Uops dispatched to specific portsApproximate counts of AVX and AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions using 256-bit operationsNumber of uops executed by dividerNumber of DTLB page walker loads that hit in the L1D and line fill bufferNumber of ITLB page walker loads that hit in the L1I and line fill bufferNumber of DTLB page walker loads that hit in the L2Number of ITLB page walker loads that hit in the L2Number of DTLB page walker loads that hit in the L3Number of ITLB page walker loads that hit in the L3Number of extended page table walks from the DTLB that hit in the L1D and line fill bufferNumber of extended page table walks from the ITLB that hit in the L1D and line fill bufferNumber of extended page table walks from the DTLB that hit in the L2Number of extended page table walks from the ITLB that hit in the L2Number of extended page table walks from the DTLB that hit in the L3Number of extended page table walks from the ITLB that hit in the L3Number of DTLB page walker loads that hit memoryNumber of ITLB page walker loads that hit memoryNumber of extended page table walks from the DTLB that hit memoryNumber of extended page table walks from the ITLB that hit memoryCycles with cacheable data read transactions in the superQ (use with HT off only)Cycles with demand code reads transactions in the superQ (use with HT off only)Cycles with demand data read transactions in the superQ (use with HT off only)Cacheable data read transactions in the superQ every cycle (use with HT off only)Code read transactions in the superQ every cycle (use with HT off only)Demand data read transactions in the superQ every cycle (use with HT off only)Outstanding RFO (store) transactions in the superQ every cycle (use with HT off only)Cycles with outstanding RFO (store) transactions in the superQ (use with HT off only)Number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abortNumber of times a class of instructions that may cause a transactional abort was executed inside a transactional regionNumber of times an instruction execution caused the supported nest count to be exceededNumber of times an instruction with HLE xbegin prefix was executed inside a RTM transactional regionNumber of times an instruction with HLE xacquire prefix was executed inside a RTM transactional regionNumber of times a transactional abort was signaled due to data conflict on a transactionally accessed addressNumber of times a transactional abort was signaled due to data capacity limitation for transactional writesABORT_HLE_STORE_TO_ELIDED_LOCKNumber of times a HLE transactional execution aborted due to a non xrelease prefixed instruction writing to an elided lock in the elision bufferABORT_HLE_ELISION_BUFFER_NOT_EMPTYNumber of times a HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zeroABORT_HLE_ELISION_BUFFER_MISMATCHNumber of times a HLE transaction execution aborted due to xrelease lock not satisfying the address and value requirements in the elision bufferABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENTNumber of times a HLE transaction execution aborted due to an unsupported read alignment from the elision bufferNumber of times a HLE clock could not be elided due to ElisionBufferAvailable being zeroNumber of times an RTM execution startedNumber of times an RTM execution successfully committedNumber of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise Event)Number of times an RTM execution aborted due to various memory eventsNumber of times an RTM execution aborted due to uncommon conditionsNumber of times an RTM execution aborted due to RTM-unfriendly instructionsNumber of times an RTM execution aborted due to incompatible memory typeNumber of times an RTM execution aborted due to none of the other 4 reasons (e.g., interrupt)Number of times an HLE execution startedNumber of times an HLE execution successfully committedNumber of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise Event)Number of times an HLE execution aborted due to various memory eventsNumber of times an HLE execution aborted due to uncommon conditionsNumber of times an HLE execution aborted due to HLE-unfriendly instructionsNumber of times an HLE execution aborted due to incompatible memory typeNumber of times an HLE execution aborted due to none of the other 4 reasons (e.g., interrupt)Request: number of L2 prefetcher requests to L3 for loadsRequest: number of bus lock and split lock requestsRequest: combination of PF_CODE_RD | DMND_CODE_RD | PF_L3_CODE_RDPF_CODE_RD:DMND_CODE_RD:PF_L3_CODE_RDRequest: combination of PF_CODE_RD | PF_L3_CODE_RDDMND_DATA_RD:DMND_RFO:DMND_CODE_RD:WB:PF_DATA_RD:PF_RFO:PF_CODE_RD:PF_L3_DATA_RD:PF_L3_RFO:PF_L3_CODE_RD:SPLIT_LOCK_UC_LOCK:STRM_ST:OTHERRequest: combination of DMND_DATA | PF_DATA_RD | PF_L3_DATA_RDDMND_DATA_RD:PF_DATA_RD:PF_L3_DATA_RDRequest: combination of DMND_RFO | PF_RFO | PF_L3_RFOSupplier: counts L3 hits in any state (M, E, S)L3_HITM:L3_HITE:L3_HITS:L3_HITFSupplier: counts L3 misses to remote DRAM with 0 hopSupplier: counts L3 misses to remote DRAM with 1 hopSupplier: counts L3 misses to remote DRAM with 2P hopsL3_MISS_LOCAL:L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2PSupplier: counts L3 misses to remote nodeL3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2PSupplier: counts L3 supplier hitSNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:SNP_HITM:SNP_NON_DRAMAll uops that actually retirednumber of retirement slots used non PEBSCycles no executable uops retired (Precise Event)Number of cycles using always true condition applied to PEBS uops retired eventCycles no executable uops retired on core (Precise Event)Number of transitions from stalled to unstalled execution (Precise Event)Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)Number of flags-merge uops being allocated. Such uops adds delayNumber of slow LEA or similar uops allocated. Such uop has 3 sources regardless if result of LEA instruction or notCounts the number of cycles no uops issued by this threadCounts the number of cycles no uops issued on this coreCycles which a Uop is executed on port 0Cycles which a Uop is executed on port 1Cycles which a Uop is executed on port 2Cycles which a Uop is executed on port 3Cycles which a Uop is executed on port 4Cycles which a Uop is executed on port 5Cycles which a Uop is executed on port 6Cycles which a Uop is executed on port 7Number of uops executed from any threadCount number of DTLB flushes of thread-specific entriesCount number of any STLB flushesCycles the Reservation Station (RS) is empty for this threadCount each time an new Last Branch Record (LBR) is insertedStall cycles caused by absence of eligible entries in Reservation Station (RS)Cycles Allocator is stalled due to Store Buffer full (not including draining from synch)Number of times any microcode assist is invoked by HW upon uop writebackDemand data read requests sent to uncore (use with HT off only)Demand code read requests sent to uncore (use with HT off only)Demand RFOs requests sent to uncore (use with HT off only)Data read requests sent to uncore (use with HT off only)Speculative cache-line split store-address uops dispatched to L1DLoad uops with true STLB miss retired to architected pathStore uops with true STLB miss retired to architected pathLoad uops with locked access retiredLine-splitted load uops retiredLine-splitted store uops retiredRetired load uops with L1 cache hits as data sourceRetired load uops with L2 cache hits as data sourceRetired load uops with L3 cache hits as data sourceRetired load uops which missed the L1DRetired load uops which missed the L2. Unknown data source excludedRetired load uops which missed the L3Retired load uops which missed L1 but hit line fill buffer (LFB)Retired load uops missing L3 cache but hitting local memoryRetired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cacheRetired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cacheLoad had HitM Response from a core on same socket (shared L3). (Non PEBSRetired load uops which data sources were hits in L3 without snoops requiredCycles there was a Nuke. Account for both thread-specific and All Thread NukesNumber of Self-modifying code (SMC) Machine Clears detectedThis event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0Core-originated cacheable demand requests missed LLC - architectural eventCore-originated cacheable demand requests that refer to LLC - architectural eventNon software-prefetch load dispatches that hit FB allocated for software prefetchNon software-prefetch load dispatches that hit FB allocated for hardware prefetchCounts the number of loads blocked by overlapping with store buffer entries that cannot be forwardednumber of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useDemand Data Read requests that access L2 cacheL2 or L3 HW prefetches that access L2 cache, including rejectsTransactions accessing L2 pipeDemand Data Read requests that miss L2 cacheDemand Data Read requests that hit L2 cacheAll demand requests that miss the L2 cacheL2 cache hits when fetching instructions, code readsRequests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cacheAll requests that miss the L2 cacheAny data read request to L2 cacheAny data RFO request to L2 cacheAny code read request to L2 cacheAll demand requests to L2 cache Number of clean L2 cachelines evicted by demandNumber of dirty L2 cachelines evicted by demandL2 cache lines in I state filling L2L2 cache lines in S state filling L2L2 cache lines in E state filling L2Number of times a demand request was blocked due to Fill Buffer (FB) unavailabilityFlushing of the Instruction TLB (ITLB) pages independent of page sizeNumber of instructions retired. General Counter - architectural eventPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise Event)Number of cycles using always true conditionPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distributionX87 FP operations retired with no exceptions. Also counts flows that have several X87 or flows that use X87 uops in the exception handlingCount number of non-delivered uops to Resource Allocation Table (RAT)Cycles the Instruction Decode Queue (IDQ) is emptyNumber of uops delivered to Instruction Decode Queue (IDQ) from MITE pathNumber of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathUops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyUops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyNumber of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITECycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE pathCycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathCycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyDeliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busyCycles Decode Stream Buffer (DSB) is delivering any UopCycles MITE is delivering any UopNumber of uops delivered to Instruction Decode Queue (IDQ) from any pathNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accessesNumber of cycles where a code-fetch stalled due to L1 instruction cache miss or an iTLB missNumber of X87 FP assists due to output valuesNumber of X87 FP assists due to input valuesCycles with any input/output SEE or FP assistsMisses in all DTLB levels that cause page walksMisses in all TLB levels causes a page walk that completes (4K)Misses in all TLB levels causes a page walk that completes (2M/4M)Misses in all TLB levels causes a page walk of any page size that completesCycles when PMH is busy with page walksMisses that miss the DTLB and hit the STLB (4K)Misses that miss the DTLB and hit the STLB (2M)Number of cache load STLB hits. No page walkDTLB misses with low part of linear-to-physical address translation missedCycles with pending L2 miss loads (must use with HT off only)Executions stalls due to pending L1D load cache missesExecution stalls due to L2 pending loads (must use with HT off only)Execution stalls due to memory subsystemCycles during which no instructions were executed in the execution stage of the pipelineCount Xclk pulses 100Mhz) when the at least one thread on the physical core is unhaltedUnhalted core cycles when the thread is in ring 0Unhalted core cycles when thread is in rings 1, 2, or 3Number of intervals between processor halts while thread is in ring 0All mispredicted macro branches (architectural event)number of near branch instructions retired that were mispredicted and takenNot taken speculative and retired mispredicted macro conditional branchesTaken speculative and retired mispredicted macro conditional branchesTaken speculative and retired mispredicted indirect branches excluding calls and returnsTaken speculative and retired mispredicted indirect branches with return mnemonicSpeculative and retired mispredicted macro conditional branchesALL_INDIRECT_JUMP_NON_CALL_RETTaken speculative and retired mispredicted indirect callsCounts all taken and not taken macro conditional branch instructionsCounts all macro direct and indirect near callsCounts all taken and not taken macro branches including far branches (architectural event)Counts the number of near ret instructions retiredCounts all not taken macro branch instructions retiredCounts the number of near branch taken instructions retiredCounts the number of far branch instructions retiredAll macro conditional nontaken branch instructionsTaken speculative and retired macro-conditional branchesTaken speculative and retired macro-conditional branch instructions excluding calls and indirectsTaken speculative and retired indirect branches excluding calls and returnsTaken speculative and retired indirect branches with return mnemonicTaken speculative and retired direct near callsSpeculative and retired macro-conditional branchesSpeculative and retired indirect branches excluding calls and returnsSpeculative and retired direct near callsAll indirect calls, including both register and memory indirectAll branch instructions executedFloating-point instructions retiredNumber of uops cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports exceeds the read bandwidth of the register file. This umask applies to instructions: DPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*Number of scalar double precision floating-point arithmetic instructions (multiply by 1 to get flops)Number of scalar single precision floating-point arithmetic instructions (multiply by 1 to get flops)Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of scalar 128-bit packed double precision floating-point arithmetic instructions (multiply by 2 to get flops)Number of scalar 128-bit packed single precision floating-point arithmetic instructions (multiply by 4 to get flops)Number of scalar 256-bit packed double precision floating-point arithmetic instructions (multiply by 4 to get flops)Number of scalar 256-bit packed single precision floating-point arithmetic instructions (multiply by 8 to get flops)Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element128B_PACKED_DOUBLE:128B_PACKED_SINGLE:256B_PACKED_SINGLE:256B_PACKED_DOUBLENumber of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element256B_PACKED_SINGLE:128B_PACKED_SINGLE:SCALAR_SINGLENumber of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementSCALAR_DOUBLE:128B_PACKED_DOUBLE:256B_PACKED_DOUBLECycles when divider is busy executing divide operationsNumber of times an instruction a xbegin instruction was executed inside HLE transactional regionNumber of times a transactional abort was signaled due to data capacity limitationNumber of uops executed per thread each cycleNumber of times the reservation station (RS) was emptyRetired load uops missing L3 cache but hitting local memory (Precise Event)Cycles when the Resource Allocation Table (RAT) external stall event is sent to the Instruction Decode Queue (IDQ) for the thread. Also includes cycles when the allocator is serving another threadPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise event)Number of FPU operations retired (instructions with no exceptions)Number of cycles where a code fetch is stalled due to L1 missMisses in all TLB levels causes a page walk that completes (4KB)Misses in all TLB levels causes a page walk that completes (2MB/4MB)Misses in all TLB levels causes a page walk that completes (1GB)Misses that miss the DTLB and hit the STLB (4KB)Misses that miss the DTLB and hit the STLB (2MB)Misses in all TLB levels causes a page walk of 2MB/4MB page sizes that completesMisses in all TLB levels causes a page walk of 1GB page sizes that completesExecutions stalls when there is at least one pending demand load requestExecutions stalls while there is at least one L1D demand load outstandingExecution stalls while there is at least one L2 demand load pending outstandingNumber of near branch instructions retired that were mispredicted and takenNumber of mispredicted ret instructions retiredTaken speculative and retired mispredicted direct returnsNumber of front-end re-steers due to BPU mispredictionSpeculative mispredicted branchesL3 miss load uops retired (Precise Event)Number of hardware interrupts received by the processorSpeculative mispredicted indirect branchesCount core cycles where the pipeline is stalled due to serialization operationsNumber of prefetch.nta instructions executedNumber of prefetch.t0 instructions executedNumber prefetch.t1 or prefetch.t2 instructions executedNumber prefetch.w instructions executedNumber of core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.Number of core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.Number of core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.Number of core cycles where the core was throttled due to a pending power level request.Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortlyCounts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortlyNumber of uncached load retiredNumber of requests for which the offcore buffer (SQ) is fullRetired instructions experiencing a critical decode stream buffer (DSB) miss. A critical DSB miss can cause stalls in the backendRetired Instructions experiencing a decode stream buffer (DSB) miss.Retired instructions experiencing ITLB true missRetired instructions experiencing L1I cache true missRetired instructions experiencing instruction L2 cache true missRetired instructions experiencing STLB (2nd level TLB) true missRetired instructions after an interval where the front-end did not deliver any uops (4 bubbles) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stallCounts instructions retired after an interval where the front-end did not deliver more than 1 uop (3 bubbles) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stallCounts instructions retired after an interval where the front-end did not deliver more than 2 uops (2 bubbles) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stallCounts instructions retired after an interval where the front-end did not deliver more than 3 uops (1 bubble) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stallCycles with 1 uop executing across all ports and Reservation Station is not emptyCycles with 2 uops executing across all ports and Reservation Station is not emptyCycles with 3 uops executing across all ports and Reservation Station is not emptyCycles with 4 uops executing across all ports and Reservation Station is not emptyCycles where the store buffer is full and no outstanding loadCycles where no uop is executed and the Reservation Station was not emptyNumber of scalar 512-bit packed double precision floating-point arithmetic instructions (multiply by 8 to get flops)Number of scalar 512-bit packed single precision floating-point arithmetic instructions (multiply by 16 to get flops)Cycles when divider is busy executing divide or square root operations on integers or floating-pointsCycles for an extended page table walk of any typeNumber of cycles the LSD delivered 4 uops which did not come from the decoderNumber of cycles the LSD delivered uops which did not come from the decoderNumber of offcore outstanding demand data read requests missing the L3 cache every cycleNumber of cycles in which at least 6 demand data read requests missing the L3CYCLES_WITH_L3_MISS_DEMAND_DATA_RDCycles with at least 1 Demand Data Read requests who miss L3 cache in the superQNumber of times an HLE execution aborted due to hardware timer expirationNumber of times an HLE execution aborted due to HLE-unfriendly instructions and certain events such as AD-assistsRequest: number of data prefetch requests to L2Request: number of RFO prefetch requests to L2Request: number of data prefetch requests for loads that end up in L3Request: number of RFO prefetch requests that end up in L3Request: number of L1 data cache hardware prefetch requests and software prefetch requestsDMND_DATA_RD:DMND_RFO:DMND_CODE_RD:OTHERDMND_DATA_RD:DMND_RFO:DMND_CODE_RD:PF_L2_DATA_RD:PF_L2_RFO:PF_L3_DATA_RD:PF_L3_RFO:PF_L1D_AND_SW:OTHERRequest: combination of DMND_DATA_RD | PF_L2_DATA_RD | PF_L3_DATA_RD | PF_L1D_AND_SWDMND_DATA_RD:PF_L2_DATA_RD:PF_L3_DATA_RD:PF_L1D_AND_SWRequest: combination of ANY_DATA_RD | PF_L2_RFO | PF_L3_RFO | DMND_RFOANY_DATA_RD:DMND_RFO:PF_L2_RFO:PF_L3_RFORequest: combination of PF_L2_DATA_RD | PF_L3_DATA_RD | PF_L1D_AND_SWPF_L2_DATA_RD:PF_L3_DATA_RD:PF_L1D_AND_SWRequest: combination of DMND_RFO | PF_L2_RFO | PF_L3_RFOSupplier: counts L3 misses (local or remote)SNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_HIT_NO_FWD:SNP_HIT_WITH_FWD:SNP_HITM:SNP_NON_DRAMNumber of blend uops issued by the Resource Allocation table (RAT) to the Reservation Station (RS) in order to preserve upper bits of vector registersNumber of uops executed per thread in each cycleNumber of cycles with at least 1 uop is executed per threadNumber of cycles with at least 2 uops are executed per threadNumber of cycles with at least 3 uops are executed per threadNumber of cycles with at least 4 uops are executed per threadNumber of uops executed from any thread in each cycleNumber of cycles with at least 1 uop is executed for any threadNumber of cycles with at least 2 uops are executed for any threadNumber of cycles with at least 3 uops are executed for any threadNumber of cycles with at least 4 uops are executed for any threadNumber of cycles with no uops executed by threadNumber of cycles with no uops executed from any threadNumber of x87 uops executed per threadCount number of retired PAUSE instructions (that do not end up with a VMEXIT to the VMM; TSX aborted instructions may be counted). This event is not supported on first SKL and KBL processorsNumber of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assistsNumber of memory transactions that reached the superqueue (SQ)Number of demand data read requests which missed the L3 cacheAll retired memory instructionsRetired load instructions with local persistent memory as the data source where the request missed all the cachesRetired load instructions which data sources missed L3 but serviced from local dramRetired load instructions which data sources missed L3 but serviced from remote dramRetired load instructions whose data sources was remote HITMRetired load instructions whose data sources was forwarded from a remote cacheRetired load instructions with remote persistent memory as the data source which missed all cachesNumber of machine clears (Nukes) of any typeDemand load dispatches that hit L1D fill buffer (FB) allocated for software prefetchDemand Data Read requests, initiated by load instructions, that hit L2 cacheRequests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cacheCounts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cacheCounts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. This is a per-core event.L1D misses outstanding duration in core cyclesNumber of times a request needed a fill buffer (FB) entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands load, store or SW prefetchCycles with L1D misses outstandingNumber of cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear eventsNumber of uops not delivered to Resource Allocation Table (RAT) per thread when backend is not stalledCount cycles front-end (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling front-endCount cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend is not stalledCount cycles with less than 2 uops delivered by the front-endCount cycles with less then 3 uops delivered by the front-endNumber of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode SequencerNumber of instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularityNumber of instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularityCycles where a code fetch is stalled due to L1 instruction cache tag missCycles where a code fetch is stalled due to L1 instruction cache missNumber of misses in all TLB levels causing a page walk of any page size that completesNumber of misses in all TLB levels causing a page walk of 4KB page size that completesNumber of misses in all TLB levels causing a page walk of 2MB/4MB page size that completesNumber of misses in all TLB levels causing a page walk of 1GB page size that completesCycles when at least one page walker is busy with a page walk request. EPT page walks are excludedCycles with at least one hardware walker active for a loadCycles when hardware page walker is busy with page walksCycles with pending L2 miss demand loads outstandingCycles with L3 cache miss demand loads outstandingCycles when memory subsystem has at least one outstanding loadExecution stalls while at least one L1D demand load cache miss is outstandingExecution stalls while at least one L2 demand load is outstandingExecution stalls while at least one L3 demand load is outstandingExecution stalls while at least one demand load is outstanding in the memory subsystemTotal execution stalls in cyclesCounts when the current privilege level transitions from ring 1, 2 or 3 to ring 0 (kernel)Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.This event counts the number of mispredicted ret instructions retired.RTM (Restricted Transaction Memory) execution.HLE (Hardware Lock Elision) execution.Floating-point instructions retired.Precise frontend retired events.Mispredicted branch instructions retired.Number of DSB to MITE switches.LSD (Loop stream detector) operations.Cycles where Allocation is stalled due to Resource Related reasons.ILD (Instruction Length Decoder) stalls.IDQ (Instruction Decoded Queue) operationsTMA slots available for an unhalted logical processor.Topdown events via PERF_METRICS MSR (Linux only). All events must be in a Linux perf_events group and SLOTS must be the first event for the kernel to program the events onto the PERF_METRICS MSR. Only SLOTS umask accepts modifiersNumber of instructions decodedNumber of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.For every cycle, increments by the number of outstanding demand data read requests pending.For every cycle, increments by the number of outstanding code read requests pending.Cycles with outstanding code read requests pending.Cycles where at least 1 outstanding Demand RFO request is pending.For every cycle, increments by the number of outstanding data read requests pending.Cycles where at least 1 outstanding data read request is pending.For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.Cycles where at least one demand data read request known to have missed the L3 cache is pending.Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.Retired instructions with at least 1 uncacheable load or Bus Lock.Number of uops decoded out of instructions exclusively fetched by decoder 0Cycles without actually retired instructions.Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution (Fixed counter 0 only. c, e, i, intx, intxcp modifiers not available)Number of instructions retired. Fixed Counter - architectural event (c, e, i, intx, intxcp modifiers not available)Number of retired NOP instructions.Cycle counts are evenly distributed between active threads in the Core.Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.Core crystal clock cycles when this thread is unhalted and the other thread is halted.Core crystal clock cycles when the thread is unhalted.Thread cycles when thread is not in halt stateReference cycles when the core is not in halt state.TMA slots where no uops were being issued due to lack of back-end resourcesTMA slots wasted due to incorrect speculations.TMA slots where no uops were being issued due to lack of front-end resources.TMA slots where instructions are retiringTMA slots available for an unhalted logical processor. Fixed counter - architectural eventTMA slots wasted due to incorrect speculation by branch mispredictionsTMA slots where no uops were being issued due to lack of back-end resources.TMA slots available for an unhalted logical processor. General counter - architectural eventThe number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.Loads blocked due to overlapping with a preceding store that cannot be forwarded.False dependencies in MOB due to partial compare on address.Loads that miss the DTLB and hit the STLB.Cycles when at least one PMH is busy with a page walk for a demand load.Number of page walks outstanding for a demand load in the PMH each cycle.Load miss in all TLB levels causes a page walk that completes (All page sizes).Page walks completed due to a demand data load to a 2M/4M page.Page walks completed due to a demand data load to a 4K page.Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.TMA slots where uops got droppedCycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.Core cycles the allocator was stalled due to recovery from earlier clear event for this threadCycles when RAT does not issue Uops to RS for the threadUops inserted at issue-stage in order to preserve upper bits of vector registers.Cycles when divide unit is busy executing divide or square root operations.SW prefetch requests that hit L2 cache. Accounts for PREFETCHNTA and PREFETCH0/1/2 instructions when FB is not full.L2 cache hits when fetching instructions, code reads.SW prefetch requests that miss L2 cache. Accounts for PREFETCHNTA and PREFETCH0/1/2 instructions when FB is not full.Demand requests that miss L2 cacheDemand Data Read miss L2, no rejectsCore cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.Core-originated cacheable demand requests missed L3 (except hardware prefetches to L3).Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3).Number of PREFETCHW instructions executed.Number of PREFETCHT1 or PREFETCHT2 instructions executed.Number of PREFETCHT0 instructions executed.Number of PREFETCHNTA instructions executed.Number of cycles a demand request has waited due to L1D due to lack of L2 resources.Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.Cycles with L1D load Misses outstanding.Number of L1D misses that are outstandingStores that miss the DTLB and hit the STLB.Cycles when at least one PMH is busy with a page walk for a store.Number of page walks outstanding for a store in the PMH each cycle.Store misses in all TLB levels causes a page walk that completes. (All page sizes)Page walks completed due to a demand data store to a 2M/4M page.Page walks completed due to a demand data store to a 4K page.Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.Counts the number of cache lines replaced in L1 data cache.Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional readsNumber of times HLE lock could not be elided due to ElisionBufferAvailable being zero.Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision bufferNumber of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision bufferSpeculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed addressNumber of times an instruction execution caused the transactional nest count supported to be exceededCounts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional regionCounts end of periods where the Reservation Station (RS) was empty.Cycles when Reservation Station (RS) is empty for the threadCycles when uops are being delivered to IDQ while MS is busyUops delivered to IDQ while MS is busyNumber of switches from DSB or MITE to the MSCycles DSB is delivering optimal number of UopsUops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pathCycles MITE is delivering optimal number of UopsUops delivered to Instruction Decode Queue (IDQ) from MITE pathCycles where a code fetch is stalled due to L1 instruction cache miss.Cycles where a code fetch is stalled due to L1 instruction cache tag miss.Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.Instruction fetch requests that miss the ITLB and hit the STLB.Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.Number of page walks outstanding for an outstanding code request in the PMH each cycle.Code miss in all TLB levels causes a page walk that completes. (All page sizes)Code miss in all TLB levels causes a page walk that completes. (2M/4M)Code miss in all TLB levels causes a page walk that completes. (4K)Stalls caused by changing prefix length of the instruction.Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalledCycles when no uops are not delivered by the IDQ when backend of the machine is not stalledUops not delivered by IDQ when backend of the machine is not stalledNumber of uops executed on port 7 and 8Number of uops executed on port 6Number of uops executed on port 5Number of uops executed on port 4 and 9Number of uops executed on port 2 and 3Number of uops executed on port 1Number of uops executed on port 0Cycles stalled due to no store buffers available. (not including draining form sync).Counts cycles where the pipeline is stalled due to serializing operations.Execution stalls while memory subsystem has an outstanding load.Cycles while memory subsystem has an outstanding load.Execution stalls while L1 cache miss demand load is outstanding.Cycles while L1 cache miss demand load is outstanding.Execution stalls while L3 cache miss demand load is outstanding.Execution stalls while L2 cache miss demand load is outstanding.Cycles while L3 cache miss demand load is outstanding.Cycles while L2 cache miss demand load is outstanding.Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.Cycles where the Store Buffer was full and no loads caused an execution stall.Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.Cycles Uops delivered by the LSD, but didn't come from the decoder.Number of Uops delivered by the LSD.DSB-to-MITE transitions count.DSB-to-MITE switch true penalty cycles.Any memory transaction that reached the SQ.Demand Data Read requests who miss L3 cacheDemand and prefetch data readsDemand RFO requests including regular RFOs, locks, ItoMCounts cacheable and non-cacheable code reads to the core.Counts the number of x87 uops dispatched.Cycles at least 4 micro-op is executed from any thread on physical core.Cycles at least 3 micro-op is executed from any thread on physical core.Cycles at least 2 micro-op is executed from any thread on physical core.Cycles at least 1 micro-op is executed from any thread on physical core.Number of uops executed on the core.Cycles where at least 4 uops were executed per-threadCycles where at least 3 uops were executed per-threadCycles where at least 2 uops were executed per-threadCycles where at least 1 uop was executed per-threadCounts number of cycles no uops were dispatched to be executed on this thread.Counts the number of uops to be executed per-thread each cycle.DTLB flush attempts of the thread-specific entriesNumber of occurrences where a microcode assist is invoked by hardware.Counts all microcode FP assists.Cycles with less than 10 actually retired uops.Cycles without actually retired uops.Self-modifying code (SMC) detected.Number of machine clears due to memory ordering conflicts.Number of machine clears (nukes) of any type.Indirect near branch instructions retired (excluding returns)Far branch instructions retired.Taken branch instructions retired.Conditional branch instructions retired.Not taken branch instructions retired.Direct and indirect near call instructions retired.Taken conditional branch instructions retired.All branch instructions retired.All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).Number of near branch instructions retired that were mispredicted and taken.Mispredicted conditional branch instructions retired.Mispredicted non-taken conditional branch instructions retired.Mispredicted indirect CALL instructions retired.number of branch instructions retired that were mispredicted and taken.All mispredicted branch instructions retired.Retired instructions after front-end starvation of at least 1 cycleRetired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.Retired instructions after front-end starvation of at least 2 cyclesRetired Instructions who experienced STLB (2nd level TLB) true miss.Retired Instructions who experienced iTLB true miss.Retired Instructions who experienced Instruction L2 Cache true miss.Retired Instructions who experienced Instruction L1 Cache true miss.Retired Instructions experiencing a critical DSB miss.Retired Instructions experiencing a DSB miss.Retired instructions after an interval where the front-end did not deliver any uops (4 bubbles) for a period determined by the fe_thres modifier (set to 1 cycle by default) and which was not interrupted by a back-end stallCounts instructions retired after an interval where the front-end did not deliver more than 1 uop (3 bubbles) for a period determined by the fe_thres modifier (set to 1 cycle by default) and which was not interrupted by a back-end stallCounts instructions retired after an interval where the front-end did not deliver more than 2 uops (2 bubbles) for a period determined by the fe_thres modifier (set to 1 cycle by default) and which was not interrupted by a back-end stallCounts instructions retired after an interval where the front-end did not deliver more than 3 uops (1 bubble) for a period determined by the fe_thres modifier (set to 1 cycle by default) and which was not interrupted by a back-end stallCounts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using this event.Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using this eventCounts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using this event.Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using this event.Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using this event.Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using this event.Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using this event.Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using this event.Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  FP instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.Number of any Vector retired FP arithmetic instructionsNumber of times an HLE execution aborted due to unfriendly events (such as interrupts).Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).Number of times an HLE execution started.Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)Number of times an RTM execution aborted due to HLE-unfriendly instructionsNumber of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)Number of times an RTM execution aborted.Number of times an RTM execution started.Number of retired PAUSE instructions.Increments whenever there is an update to the LBR array.All retired store instructions.All retired load instructions.Retired store instructions that split across a cacheline boundary.Retired load instructions that split across a cacheline boundary.Retired load instructions with locked access.Retired store instructions that miss the STLB.Retired load instructions that miss the STLB.All retired memory instructions.Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.Retired load instructions missed L3 cache as data sourcesRetired load instructions missed L2 cache as data sourcesRetired load instructions missed L1 cache as data sourcesRetired load instructions with L3 cache hits as data sourcesRetired load instructions with L2 cache hits as data sourcesRetired load instructions with L1 cache hits as data sourcesRetired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches.Retired load instructions whose data sources were hits in L3 without snoops requiredRetired load instructions whose data sources were HitM responses from shared L3Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cacheRetired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches.Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.Cache lines that have been L2 hardware prefetched but not used by demand accessesModified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.Cycles the thread is active and superQ cannot take any more entries.Counts bus locks, accounts for cache line split locks and UC locks.Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.Counts hardware prefetch (which bring data to L2) that have any type of response.READS_TO_CORE_LOCAL_SOCKET_PMMCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.READS_TO_CORE_LOCAL_SOCKET_DRAMCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.READS_TO_CORE_L3_MISS_LOCAL_SOCKETCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.READS_TO_CORE_SNC_CACHE_HIT_WITH_FWDCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.DEMAND_CODE_RD_SNC_CACHE_HIT_WITH_FWDCounts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.DEMAND_RFO_SNC_CACHE_HIT_WITH_FWDCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.DEMAND_DATA_RD_SNC_CACHE_HIT_WITH_FWDCounts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.Counts streaming stores that missed the local socket's L1, L2, and L3 caches.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.READS_TO_CORE_REMOTE_CACHE_SNOOP_FWDCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).READS_TO_CORE_REMOTE_CACHE_SNOOP_HIT_WITH_FWDCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.READS_TO_CORE_REMOTE_CACHE_SNOOP_HITMCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.READS_TO_CORE_L3_HIT_SNOOP_HIT_WITH_FWDCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.READS_TO_CORE_L3_HIT_SNOOP_HITMCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.READS_TO_CORE_L3_HIT_SNOOP_HIT_NO_FWDCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.HWPF_L1D_AND_SWPF_L3_MISS_LOCALCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.Counts demand data reads that were supplied by PMM.Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.Counts demand data reads that were supplied by PMM attached to another socket.Counts demand data reads that were supplied by DRAM.DEMAND_DATA_RD_REMOTE_CACHE_SNOOP_HIT_WITH_FWDCounts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.DEMAND_DATA_RD_REMOTE_CACHE_SNOOP_HITMCounts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.Counts demand data reads that were supplied by DRAM attached to another socket.Counts hardware prefetches to the L3 only that have any type of response.Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.Counts streaming stores that have any type of response.Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.Counts demand data reads that have any type of response.DEMAND_CODE_RD_L3_HIT_SNOOP_HITMCounts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.DEMAND_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWDCounts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.DEMAND_DATA_RD_L3_HIT_SNOOP_HITMCounts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.DEMAND_DATA_RD_L3_HIT_SNOOP_HIT_NO_FWDCounts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.Counts streaming stores that DRAM supplied the request.Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.Counts hardware prefetch data reads (which bring data to L2)  that DRAM supplied the request.Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.Counts demand data reads that DRAM supplied the request.Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.Counts streaming stores that was not supplied by the L3 cache.Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.Counts hardware prefetch data reads (which bring data to L2)  that was not supplied by the L3 cache.Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.Counts demand data reads that was not supplied by the L3 cache.Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.HWPF_L2_DATA_RD_L3_HIT_SNOOP_SENTCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent.DEMAND_CODE_RD_L3_HIT_SNOOP_SENTCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.DEMAND_DATA_RD_L3_HIT_SNOOP_SENTCounts demand data reads that hit a cacheline in the L3 where a snoop was sent.HWPF_L1D_AND_SWPF_ANY_RESPONSECounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.Counts hardware prefetch data reads (which bring data to L2)  that have any type of response.Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.HWPF_L1D_AND_SWPF_L3_HIT_SNOOP_MISSCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.HWPF_L1D_AND_SWPF_L3_HIT_SNOOP_NOT_NEEDEDCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.HWPF_L2_RFO_L3_HIT_SNOOP_HIT_NO_FWDCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.HWPF_L2_RFO_L3_HIT_SNOOP_NOT_NEEDEDCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent or not.HWPF_L2_DATA_RD_L3_HIT_SNOOP_HITMCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.HWPF_L2_DATA_RD_L3_HIT_SNOOP_HIT_NO_FWDCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.HWPF_L2_DATA_RD_L3_HIT_SNOOP_MISSCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.HWPF_L2_DATA_RD_L3_HIT_SNOOP_NOT_NEEDEDCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.DEMAND_CODE_RD_L3_HIT_SNOOP_HIT_NO_FWDCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.DEMAND_CODE_RD_L3_HIT_SNOOP_MISSCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.DEMAND_CODE_RD_L3_HIT_SNOOP_NOT_NEEDEDCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.DEMAND_RFO_L3_HIT_SNOOP_HIT_NO_FWDCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.DEMAND_RFO_L3_HIT_SNOOP_NOT_NEEDEDCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.DEMAND_DATA_RD_L3_HIT_SNOOP_MISSCounts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.DEMAND_DATA_RD_L3_HIT_SNOOP_NOT_NEEDEDCounts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.integer ADD, SUB, SAD 128-bit vector instructions.Retired memory uops for any accessRetired instructions with at least 1 uncacheable load or lock.Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.Retired Instructions who experienced a critical DSB miss.LSD (Loop Stream Detector) operations.Reservation Station (RS) activity.This event is deprecated. Refer to new event RS.EMPTY_COUNTIDQ (Instruction Decoded Queue) operations.Number of instructions retired.Number of all retired NOP instructions.Precise instruction retired with PEBS precise-distributionIterations of Repeat string retired instructions.Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.Reference cycles when the core is not in halt state (Fixed Counter 2).Reference cycles when the core is not in halt state (Programmable Counter).Core cycles when the thread is not in halt stateTMA slots wasted due to lack of uops to decode due to code fetch latencies.TMA slots where instructions with 2+ uops retired.TMA slots wasted due to back-end waiting for memory.Load miss in all TLB levels causes a page walk that completes. (All page sizes)Page walks completed due to a demand data load to a 1G page.Page walks completed due to a demand data store to a 1G page.Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.Cycles where at least 1 outstanding demand data read request is pending.Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.Cacheable and noncacheable code read requestsCounts demand data read requests that miss the L3 cache.SW prefetch requests that hit L2 cache.SW prefetch requests that miss L2 cache.Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fillCycles the uncore cannot take further requestsCore-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.Completed demand load uops that miss the L1 d-cache.Execution stalls while L2 cache miss demand cacheable load request is outstandingExecution stalls while L3 cache miss demand cacheable load request is outstandingInstruction decoders utilized in a cycleCycles the Microcode Sequencer is busy.This event is deprecated. Refer to new event RS.EMPTYCycles when Reservation Station (RS) is empty for the thread.This event counts the cycles the integer divider is busy.Uops executed on ports 2, 3 and 10Uops executed on ports 4 and 9Uops executed on ports 5 and 11Uops executed on ports 7 and 8Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.Number of branch instructions retired that were mispredicted and taken.Miss-predicted near indirect branch instructions retired (excluding returns)Mispredicted indirect CALL retired.This event counts the number of mispredicted ret instructions retired. Non PEBSRetired Instructions who experienced DSB miss.Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt)Retired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility.Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.integer ADD, SUB, SAD 256-bit vector instructions.DEMAND_DATA_RD_LOCAL_SOCKET_PMMCounts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.Counts data load hardware prefetch requests to the L1 data cache that have any type of response.Counts hardware prefetches (which bring data to L2) that have any type of response.Counts writebacks of modified cachelines and streaming stores that have any type of response.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.  It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.Clears due to Unknown Branches.Counts number arithmetic operations.Precise frontend retired eventsIDQ (Instruction Decoded Queue) bubbles.Integer ADD, SUB, SAD 128-bit vector instructions.Retired load instructions whose data sources were L3 hit.Retired load instructions which data sources missed L3.Miscellaneous load retired instructions.Miscellaneous retired operations.Retired uops except the last uop of each instruction.This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance  for example, as measured by the instructions-per-cycle metric.Number of non dec-by-all uops decoded by decoderThis event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.Cycles when RS was empty and a resource allocation stall is assertedCycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.Cycles where data return is pending for a Demand Data Read request who miss L3 cache.Store Read transactions pending for off-core. Highly correlated.Cacheable and Non-Cacheable code read requestsCounts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.Retired memory store access operations. A PDist event for PEBS Store Latency Facility.Retired load instructions that hit the STLB.Retired store instructions that hit the STLB.Execution stalls while L2 cache miss demand cacheable load request is outstanding.Execution stalls while L3 cache miss demand cacheable load request is outstanding.Demand Data Read access L2 cacheDemand Data Read miss L2 cacheAll requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS]All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]Integer ADD, SUB, SAD 256-bit vector instructions.Bubble cycles of BAClear (Unknown Branch).Number of instructions retired. Fixed Counter - architectural eventCycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyI-Cache miss too close to Code Prefetch InstructionMispredicted Retired ANT branchesADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. The event also counts for Machine Ordering count.This event counts the cycles the floating point divider is busy.Number of Joules consumed by all cores and Last level cache on the package. Unit is 2^-32 JoulesNumber of Joules consumed by the DRAM. Unit is 2^-32 JoulesNumber of Joules consumed by all cores on the package. Unit is 2^-32 JoulesNumber of Joules consumed by the builtin GPU. Unit is 2^-32 JoulesNumber of Joules consumed by the builtin PSYS. Unit is 2^-32 Joules%s (%s.%d): no default found for event %s unit mask group %d (max_grpid=%d, i=%d)
%s (%s.%d): invalid thread id, must be < 1%s (%s.%d): invalid nf,  0 < nf < 256
%s (%s.%d): address filter 40bits max
%s (%s.%d): dnid must be [0-15]
%s (%s.%d): rcsnid must be [0-15]
%s (%s.%d): event %s invalid attribute %d
%s (%s.%d): event has umasks but none specified
%s (%s.%d): using nf= on an umask which does not require it
%s (%s.%d): umask2=0x%lx umask1=0x%lx
%s (%s.%d): unknown attribute %d for event %s
[UNC=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
core id filter, includes non-thread data in bit 4 [0-15]node id bitmask filter [0-255]physical address matcher [40 bits]core id filter, includes non-thread data in bit 5 [0-63]destination RCS Node id [0-15][UNC_CBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d tid_en=%d] %s
[UNC_CBOX_FILTER=0x%lx tid=%d core=0x%x nid=0x%x state=0x%x opc=0x%x]
Intel Sandy Bridge-EP C-Box 7 uncoreIntel Sandy Bridge-EP C-Box 6 uncoreIntel Sandy Bridge-EP C-Box 5 uncoreIntel Sandy Bridge-EP C-Box 4 uncoreIntel Sandy Bridge-EP C-Box 3 uncoreIntel Sandy Bridge-EP C-Box 2 uncoreIntel Sandy Bridge-EP C-Box 1 uncoreIntel Sandy Bridge-EP C-Box 0 uncoreCounter 0 occupancy. Counts the occupancy related information by filtering CB0 occupancy count captured in counter 0.Cache lookups. Counts number of times the LLC is accessed from L2 for code, data, prefetches (Must set filter mask bit 0 and select )Address ring in use. Counts number of cycles ring is being used at this ring stopAcknowledgment ring in use. Counts number of cycles ring is being used at this ring stopBus or Data ring in use. Counts number of cycles ring is being used at this ring stopNumber of LLC responses that bounced in the ringInvalidate ring in use. Counts number of cycles ring is being used at this ring stopIngress arbiter blocking cyclesCounts the number of ring transactions from Cachebo to AD ringCounts the number of ring transactions from Cachebo to AK ringCounts the number of ring transactions from Cachebo to BL ringCounts the number of ring transactions from Cachebo to IV ringCounts the number of ring transactions from Corebo to AD ringCounts the number of ring transactions from Corebo to AK ringCounts the number of ring transactions from Corebo to BL ringNumber of outstanding eviction transactions in the TORNumber of outstanding miss requests in the TORNumber of TOR entries that match a NID and an opcode (must provide opc_* umask)Number of NID-matched outstanding requests in the TOR (must provide nf=X modifier)Number of NID-matched outstanding requests in the TOR (must provide a nf=X modifier)Number of NID-matched outstanding miss requests in the TOR (must provide a nf=X modifier)Number of NID-matched outstanding miss requests in the TOR that an opcode (must provide nf=X modifier and opc_* umask)Number of NID-matched TOR entries that an opcode (must provide nf=X modifier and opc_* umask)Number of TOR entries that match an opcode (must provide opc_* umask)Demand data RFO (combine with any OPCODE umask)Demand code read (combine with any OPCODE umask)Demand data read (combine with any OPCODE umask)Partial reads (UC) (combine with any OPCODE umask)Full Stream store (combine with any OPCODE umask)Partial Stream store (combine with any OPCODE umask)Prefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)Prefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)Prefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)PCIe write (non-allocating) (combine with any OPCODE umask)PCIe UC read (combine with any OPCODE umask)PCIe write (allocating) (combine with any OPCODE umask)PCIe read current (combine with any OPCODE umask)Request writeback modified invalidate line (combine with any OPCODE umask)Request writeback modified set to exclusive (combine with any OPCODE umask)Request invalidate line (combine with any OPCODE umask)PCIe non-snoop read (combine with any OPCODE umask)PCIe non-snoop write (partial) (combine with any OPCODE umask)PCIe non-snoop write (full) (combine with any OPCODE umask)Number of Evictions transactions inserted into TORNumber of miss requests inserted into the TORNumber of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)Number of NID-matched transactions inserted into the TOR (must provide nf=X modifier)Number of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)Number of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)Number of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)Number of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)Number of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)Number of transactions inserted into the TOR that match an opcode (must provide opc_* umask)Number of write transactions inserted into the TORCounts the number of allocated into the IRQ ordering FIFOIrq externally starved, therefore blocking the IPQIPQ externally starved, therefore blocking the IRQISMQ externally starved, therefore blocking both IRQ and IPQUp and Even ring polarity filterUp and odd ring polarity filterDown and even ring polarity filterDown and odd ring polarity filterVictimized Lines matching the NID filter (must provide nf=X modifier)Write requests. Includes all write transactions (cached, uncached)Match a given RTID destination NID (must provide nf=X modifier)[UNC_HA=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
[UNC_HA_ADDR=0x%lx lo_addr=0x%x hi_addr=0x%x]
Intel Sandy Bridge-EP HA uncoreUNC_H_DIRECT2CORE_CYCLES_DISABLEDCycles when Direct2Core was DisabledUNC_H_DIRECT2CORE_TXN_OVERRIDENumber of Reads that had Direct2Core OverriddenCycles without QPI Ingress CreditsHA to iMC Full Line Writes IssuedUNC_H_RPQ_CYCLES_NO_REG_CREDITSiMC RPQ Credits Empty - RegularHA Requests to a TAD Region - Group 0HA Requests to a TAD Region - Group 1Outbound NDR Ring TransactionsOutbound DRS Ring Transactions to CacheUNC_H_WPQ_CYCLES_NO_REG_CREDITSHA iMC CHN0 WPQ Credits Empty - RegularCounts data being sent to the cacheCounts data being sent directly to the requesting coreCounts data being sent to a remote socket over QPICounts cycles from both schedulersCounts cycles from scheduler bank 0Counts cycles from scheduler bank 1Counts cycles full from both schedulersCounts cycles full from scheduler bank 0Counts cycles full from scheduler bank 1Counts outbound snoops send on the ringCounts incoming read requests. Good proxy for LLC read misses, incl. RFOsNumber of cycles that we are handling conflictsNumber of cycles that we are not handling conflictsIntel Sandy Bridge-EP IMC3 uncoreIntel Sandy Bridge-EP IMC2 uncoreIntel Sandy Bridge-EP IMC1 uncoreIntel Sandy Bridge-EP IMC0 uncoreDRAM RD_CAS and WR_CAS Commands.Number of DRAM Refreshes IssuedUNC_M_POWER_CRITICAL_THROTTLE_CYCLESRead Pending Queue Full CyclesRead Pending Queue AllocationsWrite Pending Queue Full CyclesWrite Pending Queue AllocationsCounts number of DRAM precharge commands sent on this channel as a result of the page close counter expiringCounts number of DRAM precharge commands sent on this channel as a result of page missesCounts read over read preemptionsCounts read over write preemptionsCounts cycles in ISOCH Major modeCounts cycles in Partial Major modeCounts cycles in Read Major modeCounts cycles in Write Major modeCounts total number of DRAM CAS commands issued on this channelCounts all DRAM reads on this channel, incl. underfillsCounts number of DRAM read CAS commands issued on this channel, incl. regular read CAS and those with implicit prechargeCounts number of underfill reads issued by the memory controllerCounts number of DRAM write CAS commands on this channelCounts Number of opportunistic DRAM write CAS commands issued on this channelCounts number of DRAM write CAS commands issued on this channel while in Write-Major mode[UNC_PCU=0x%lx event=0x%x occ_sel=0x%x en=%d inv=%d edge=%d thres=%d occ_inv=%d occ_edge=%d] %s
[UNC_PCU_FILTER=0x%lx band0=%u band1=%u band2=%u band3=%u]
Intel Sandy Bridge-EP PCU uncoreCore C State Transition CyclesCurrent Strongest Upper Limit CyclesUNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLESThermal Strongest Upper Limit CyclesOS Strongest Upper Limit CyclesPower Strongest Upper Limit CyclesIO P Limit Strongest Lower Limit CyclesPerf P Limit Strongest Lower Limit CyclesCycles spent changing FrequencyUNC_P_MEMORY_PHASE_SHEDDING_CYCLESTotal Core C State Transition CyclesUNC_P_VOLT_TRANS_CYCLES_CHANGEUNC_P_VOLT_TRANS_CYCLES_DECREASEUNC_P_VOLT_TRANS_CYCLES_INCREASE[UNC_QPI=0x%lx event=0x%x sel_ext=%d umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
Intel Sandy Bridge-EP QPI1 uncoreIntel Sandy Bridge-EP QPI0 uncoreUNC_Q_RXL_CREDITS_CONSUMED_VN0UNC_Q_RXL_CREDITS_CONSUMED_VNARx Flit Buffer Allocations - DRSRx Flit Buffer Allocations - HOMRx Flit Buffer Allocations - NCBRx Flit Buffer Allocations - NCSRx Flit Buffer Allocations - NDRRx Flit Buffer Allocations - SNPTx Flit Buffer Cycles not EmptyUNC_Q_VNA_CREDIT_RETURN_OCCUPANCYVNA Credits Pending Return - OccupancyNumber of non-coherent bypass flitsNumber of non-coherent data flitsNumber of bypass non-data flitsNumber of non-coherent standard (NCS) flitsNumber of flits received over Non-data response (NDR) channelNumber of flits received on the Non-data response (NDR) channel)Number of flits over QPI on the Data Response (DRS) channelNumber of data flits over QPI on the Data Response (DRS) channelNumber of protocol flits over QPI on the Data Response (DRS) channelNumber of flits over QPI on the home channelNumber of non-request flits over QPI on the home channelNumber of data requests over QPI on the home channelNumber of snoop requests flits over QPINumber of flits over QPI that do not hold protocol payloadNumber of non-NULL non-data flits over QPINumber of times VN0 consumed for DRS message classNumber of times VN0 consumed for HOM message classNumber of times VN0 consumed for NCB message classNumber of times VN0 consumed for NCS message classNumber of times VN0 consumed for NDR message classNumber of times VN0 consumed for SNP message classNumber of spawn failures due to lack of Egress creditsNumber of spawn failures due to lack of Egress credit and route-back table (RBT) bit was not setNumber of spawn failures because route-back table (RBT) specified that the transaction should not trigger a direct2core transactionIntel Sandy Bridge-EP U-Box uncoreIntel Sandy Bridge-EP R2PCIe uncoreCounter-clockwise and even ring polarityCounter-clockwise and odd ring polarityCounter-clockwise with any polarityany direction and any polarityIntel Sandy Bridge-EP R3QPI1 uncoreIntel Sandy Bridge-EP R3QPI0 uncoreVN0 Credit Acquisition Failed on DRSCycles with no VNA credits availableCycles with 1 or more VNA credits in useCounter-Clockwise and even ring polarityCounter-Clockwise and odd ring polarity[UNC_CBOX_FILTER0=0x%lx tid=%d core=0x%x state=0x%x]
[UNC_CBOX_FILTER1=0x%lx nid=%d opc=0x%x nc=0x%x isoc=0x%x]
Intel Ivy Bridge-EP C-Box 14 uncoreIntel Ivy Bridge-EP C-Box 13 uncoreIntel Ivy Bridge-EP C-Box 12 uncoreIntel Ivy Bridge-EP C-Box 11 uncoreIntel Ivy Bridge-EP C-Box 10 uncoreIntel Ivy Bridge-EP C-Box 9 uncoreIntel Ivy Bridge-EP C-Box 8 uncoreIntel Ivy Bridge-EP C-Box 7 uncoreIntel Ivy Bridge-EP C-Box 6 uncoreIntel Ivy Bridge-EP C-Box 5 uncoreIntel Ivy Bridge-EP C-Box 4 uncoreIntel Ivy Bridge-EP C-Box 3 uncoreIntel Ivy Bridge-EP C-Box 2 uncoreIntel Ivy Bridge-EP C-Box 1 uncoreIntel Ivy Bridge-EP C-Box 0 uncoreAcknowledgement ring in use. Counts number of cycles ring is being used at this ring stopCounts the number of times when a SNoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodingsCounts the number of times a USWC write (WCIL(F)) transaction hits in the LLC in M state, triggering a WBMTOI followed by the USWC write. This occurs when there is WC aliasingCounts the number of times that an RFO hits in S state. This is useful for determining if it might be good for a workload to use RSPIWB instead of RSPSWBCounts the number of ring transactions from Cachebo ton IV ringNumber of write transactions in the TOR. Does not include RFO, but actual operations that contain data being sent from the coreNumber of opcode-matched transactions in the TOR that are satisfied by locally homed memoryNumber of miss opcode-matched transactions in the TOR that are satisfied by locally homed memoryNumber of transactions in the TOR that are satisfied by locally homed memoryNumber of miss transactions in the TOR that are satisfied by locally homed memoryNumber of NID-matched write transactions in the TOR (must provide a nf=X modifier)Number of opcode-matched transactions in the TOR that are satisfied by remote caches or memoryNumber of miss opcode-matched transactions in the TOR that are satisfied by remote caches or memoryNumber of transactions in the TOR that are satisfied by remote caches or memoryNumber of miss transactions inserted into the TOR that are satisfied by remote caches or memoryNumber of transactions inserted in TORNumber of opcode-matched transactions inserted into the TOR that are satisfied by locally homed memoryNumber of miss opcode-matched transactions inserted into the TOR that are satisfied by locally homed memoryNumber of transactions inserted into the TOR that are satisfied by locally homed memoryNumber of miss transactions inserted into the TOR that are satisfied by locally homed memoryNumber of opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memoryNumber of miss opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memoryNumber of transactions inserted into the TOR that are satisfied by remote caches or memoryIRQ is blocking the ingress queue and causing starvationUp and Even ring polarity filter on virtual ring 0Up and odd ring polarity filter on virtual ring 0Down and even ring polarity filter on virtual ring 0Down and odd ring polarity filter on virtual ring 0Up and Even ring polarity filter on virtual ring 1Up and odd ring polarity filter on virtual ring 1Down and even ring polarity filter on virtual ring 1Down and odd ring polarity filter on virtual ring 1Intel Ivy Bridge-EP HA 1 uncoreIntel Ivy Bridge-EP HA 0 uncoreHA to IMC Full Line Writes IssuedHA to IMC normal priority reads issuedOutbound Ring Transactions on AKBackup Tracker cycles not emptyAD QPI Link 2 credit accumulatorBL QPI Link 2 credit accumulatorDirectory latency optimization data return path takenSnoop responses received localNumber of outbound NDR (non-data response) transactions send on the AK ring. AK NDR is used for messages to the local socketNumber of outbound CDR transactions send on the AK ring to CBONumber of outbound CDR transactions send on the AK ring to QPIFilters for snoop responses of RspI. RspI is returned when the remote cache does not have the data or when the remote cache silently evicts data (e.g. RFO hit non-modified line)Filters for snoop responses of RspS. RspS is returned when the remote cache has the data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E-stateFilters for snoop responses of RspIFwd. RspIFwd is returned when the remote cache agent forwards data and the requesting agent is able to acquire the data in E or M state. This is commonly returned with RFO transacations. It can be either HitM or HitFEFilters for snoop responses of RspSFwd. RspSFwd is returned when the remote cache agent forwards data  but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F stateFilters for snoop responses of RspIWB or RspSWB. This is returned when a non-RFO requests hits in M-state. Data and code reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownershipFilters for snoop responses of RspxFwdxWB. This snoop response is only used in 4s systems. It is used when a snoop HITM in a remote caching agent and it directly forwards data to a requester and simultaneously returns data to the home to be written back to memoryFilters for snoop responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CMAs that caching agent. This triggers the conflict resolution hardware. This covers both RspConflct and RspCnflctWBIFilters all other snoop responsesCounter-clockwise and even ring polarity on virtual ring 0Counter-clockwise and odd ring polarity on virtual ring 0Counter-clockwise and even ring polarity on virtual ring 1Counter-clockwise and odd ring polarity on virtual ring 1Clockwise and even ring polarity on virtual ring 1Clockwise and odd ring polarity on virtual ring 1Clockwise with any polarity on either virtual ringsCounter-clockwise with any polarity on either virtual ringsCounts incoming read requests coming from local socket. Good proxy for LLC read misses, incl. RFOs from the local socketCounts incoming read requests coming from remote socket. Good proxy for LLC read misses, incl. RFOs from the remote socketCounts incoming writes from local socketCounts incoming writes from remote socketCounts InvItoE coming from local socketCounts InvItoE coming from remote socketCount every last conflictor in conflict chain. Can be used to compute average conflict chain lengthCount the number of cmp_fwd. This gives the number of late conflictsIntel Iyy Bridge-EP IMC7 uncoreIntel Iyy Bridge-EP IMC6 uncoreIntel Iyy Bridge-EP IMC5 uncoreIntel Iyy Bridge-EP IMC4 uncoreIntel Iyy Bridge-EP IMC3 uncoreIntel Iyy Bridge-EP IMC2 uncoreIntel Iyy Bridge-EP IMC1 uncoreIntel Iyy Bridge-EP IMC0 uncoreIMC Uncore clockticks (fixed counter)IMC Uncore clockticks (generic counters)VMSE MXB write buffer occupancyTransitions from WMM to RMM because of low thresholdNot getting the requested major modeTransition from WMM to RMM because of starve counterRead CAS issued with low priorityRead CAS issued with medium priorityRead CAS issued with high priorityRead CAS issued with panic non isoch priority (starved)ACT command issued by 2 cycle bypassCAS command issued by 2 cycle bypassPRE command issued by 2 cycle bypassCounts Number of opportunistic DRAM read CAS commands issued on this channelCounts number of DRAM read CAS commands issued on this channel while in Write-Major mode[UNC_PCU=0x%lx event=0x%x sel_ext=%d occ_sel=0x%x en=%d edge=%d thres=%d occ_inv=%d occ_edge=%d] %s
Intel Ivy Bridge-EP PCU uncoreCore 0 C State Transition CyclesCore 1 C State Transition CyclesCore 2 C State Transition CyclesCore 3 C State Transition CyclesCore 4 C State Transition CyclesCore 5 C State Transition CyclesCore 6 C State Transition CyclesCore 7 C State Transition CyclesCore 8 C State Transition CyclesCore 9 C State Transition CyclesUNC_P_CORE10_TRANSITION_CYCLESCore 10 C State Transition CyclesUNC_P_CORE11_TRANSITION_CYCLESCore 11 C State Transition CyclesUNC_P_CORE12_TRANSITION_CYCLESCore 12 C State Transition CyclesUNC_P_CORE13_TRANSITION_CYCLESCore 13 C State Transition CyclesUNC_P_CORE14_TRANSITION_CYCLESCore 14 C State Transition CyclesUNC_P_DELAYED_C_STATE_ABORT_CORE0UNC_P_DELAYED_C_STATE_ABORT_CORE1UNC_P_DELAYED_C_STATE_ABORT_CORE2UNC_P_DELAYED_C_STATE_ABORT_CORE3UNC_P_DELAYED_C_STATE_ABORT_CORE4UNC_P_DELAYED_C_STATE_ABORT_CORE5UNC_P_DELAYED_C_STATE_ABORT_CORE6UNC_P_DELAYED_C_STATE_ABORT_CORE7UNC_P_DELAYED_C_STATE_ABORT_CORE8UNC_P_DELAYED_C_STATE_ABORT_CORE9UNC_P_DELAYED_C_STATE_ABORT_CORE10Deep C state rejection Core 10UNC_P_DELAYED_C_STATE_ABORT_CORE11Deep C state rejection Core 11UNC_P_DELAYED_C_STATE_ABORT_CORE12Deep C state rejection Core 12UNC_P_DELAYED_C_STATE_ABORT_CORE13Deep C state rejection Core 13UNC_P_DELAYED_C_STATE_ABORT_CORE14Deep C state rejection Core 14Package C state exit latency. Counts cycles the package is transitioning from C2 to C3Intel Ivy Bridge-EP QPI2 uncoreIntel Ivy Bridge-EP QPI1 uncoreIntel Ivy Bridge-EP QPI0 uncoreUNC_Q_RXL_CREDITS_CONSUMED_VN1UNC_Q_TXR_AD_HOM_CREDIT_ACQUIREDR3QPI Egress credit occupancy AD HOMUNC_Q_TXR_AD_HOM_CREDIT_OCCUPANCYUNC_Q_TXR_AD_NDR_CREDIT_ACQUIREDR3QPI Egress credit occupancy AD NDRUNC_Q_TXR_AD_NDR_CREDIT_OCCUPANCYUNC_Q_TXR_AD_SNP_CREDIT_ACQUIREDR3QPI Egress credit occupancy AD SNPUNC_Q_TXR_AD_SNP_CREDIT_OCCUPANCYUNC_Q_TXR_AK_NDR_CREDIT_ACQUIREDR3QPI Egress credit occupancy AK NDRUNC_Q_TXR_AK_NDR_CREDIT_OCCUPANCYUNC_Q_TXR_BL_DRS_CREDIT_ACQUIREDR3QPI Egress credit occupancy BL DRSUNC_Q_TXR_BL_DRS_CREDIT_OCCUPANCYUNC_Q_TXR_BL_NCB_CREDIT_ACQUIREDR3QPI Egress credit occupancy BL NCBUNC_Q_TXR_BL_NCB_CREDIT_OCCUPANCYUNC_Q_TXR_BL_NCS_CREDIT_ACQUIREDR3QPI Egress credit occupancy BL NCSUNC_Q_TXR_BL_NCS_CREDIT_OCCUPANCYNumber of times VN1 consumed for DRS message classNumber of times VN1 consumed for HOM message classNumber of times VN1 consumed for NCB message classNumber of times VN1 consumed for NCS message classNumber of times VN1 consumed for NDR message classNumber of times VN1 consumed for SNP message classNumber of spawn failures due to RBT tag not matching although the valid bit was set and there was enough Egress creditsNumber of spawn failures due to RBT tag not matching and they were not enough Egress credits. The valid bit was setNumber of spawn failures due to RBT tag not matching, the valid bit was not set but there were enough Egress creditsNumber of spawn failures due to RBT tag not matching, the valid bit was not set and there were not enough Egress creditsIntel Ivy Bridge-EP U-Box uncoreNumber of cycles asserted to ACKNumber of cycles ACK to deassertIntel Ivy Bridge-EP R2PCIe uncoreany direction and any polarity on any virtual ringIntel Ivy Bridge-EP R3QPI2 uncoreIntel Ivy Bridge-EP R3QPI1 uncoreIntel Ivy Bridge-EP R3QPI0 uncoreAD counter-clockwise Egress queueBL counter-clockwise Egress queueCounter-Clockwise and even ring polarity on virtual ring 0Counter-Clockwise and odd ring polarity on virtual ring 0[UNC_IRP=0x%lx event=0x%x umask=0x%x en=%d edge=%d thres=%d] %s
Intel Ivy Bridge-EP IRP uncoreUNC_I_CACHE_ACK_PENDING_OCCUPANCYOutstanding write ownership occupancyUNC_I_TXR_AD_STALL_CREDIT_CYCLESUNC_I_TXR_BL_STALL_CREDIT_CYCLESOutbound request queue occupancyUNC_I_WRITE_ORDERING_STALL_CYCLESNumber of read requests (not including read prefetches)Number of write requests. Each write should have a prefetch, so there is no need to explicitly track these requestsNumber of request that lost ownership as a result of a tickleNumber of cases when a tickle was received but the request was at the head of the queue in the switch. In this case data is returned rather than releasing ownershipTrack all requests from any source portNumber of time when it is not possible to merge two conflicting requests, a stall event occursNumber of times when two requests to the same address from the same source are received back to back, it is possible to merge themIntel Haswell-EP C-Box 17 uncoreIntel Haswell-EP C-Box 16 uncoreIntel Haswell-EP C-Box 15 uncoreIntel Haswell-EP C-Box 14 uncoreIntel Haswell-EP C-Box 13 uncoreIntel Haswell-EP C-Box 12 uncoreIntel Haswell-EP C-Box 11 uncoreIntel Haswell-EP C-Box 10 uncoreIntel Haswell-EP C-Box 9 uncoreIntel Haswell-EP C-Box 8 uncoreIntel Haswell-EP C-Box 7 uncoreIntel Haswell-EP C-Box 6 uncoreIntel Haswell-EP C-Box 5 uncoreIntel Haswell-EP C-Box 4 uncoreIntel Haswell-EP C-Box 3 uncoreIntel Haswell-EP C-Box 2 uncoreIntel Haswell-EP C-Box 1 uncoreIntel Haswell-EP C-Box 0 uncoreNumber of cycles in which the local distress or incoming distress signals are asserted (FaST). Incoming distress includes both up and downCounts the number of clean victims with raw CV=0 (core valid)Counts the number of Demand Data Read requests hitting non-modified state lines with raw CV=0 (core valid)Write Invalidate Line (Partial) (combine with any OPCODE umask)PCIe write (partial, non-allocating) - partial line MMIO write transactions from IIO (P2P). Not used for coherent transacions. Uncacheable. (combine with any OPCODE umask)PCIe write (full, non-allocating) - full line MMIO write transactions from IIO (P2P). Not used for coherent transacions. Uncacheable. (combine with any OPCODE umask)Request invalidate line. Request exclusive ownership of the line  (combine with any OPCODE umask)Count number of time that a request from the ISMQ was retried because it lacked credits to send an AD packet to SBOCount number of time that a request from the ISMQ was retried because it lacked credits to send an BL packet to SBOCount number of times that a request from the ISMQ was retried filtered by the target NodeIdCount number of time that a request from the IRQ was retried because it lacked credits to send an AD packet to SBOCount number of time that a request from the IRQ was retried because it lacked credits to send an BL packet to SBOCount number of times that a request from the IRQ was retried filtered by the target NodeIdCount number of time that a request from the IPQ was retried because it lacked credits to send an AD packet to SBOCount number of times that a request from the IPQ was retried filtered by the target NodeIdup or down ring polarity filterCacheline is modified but never written, was forwarded in modified stateNumber of PV bits set on HitMe cache hitsNumber of accesses to HitMe cacheNumber of reads when the snoops was on the critical path to the data returnNumber of cycles when one or more snoops are outstandingTracker snoops outstanding accumulatorUNC_H_TRACKER_PENDING_OCCUPANCYData pending occupancy accumulatorNumber of hits with opcode RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvToENumber of hits with opcode WbToMtoINumber of hits with opcode AckCnfltWbINumber of hits with opcode WbMtoE or WbMtoSNumber of hits with HOM requestsNumber of hits with opcode RspIFwd, RspIFwdWb for remore requestsNumber of hits with opcode RspIFwd, RspIFwdWb for local requestsNumber of hits with opcode RsSFwd, RspSFwdWbNumber of hits with opcode RspI, RspIWb, RspSWb, RspCnflt, RspCnfltWbINumber of hits for invalidationsNumber of hits for allocationsUNC_P_CORE15_TRANSITION_CYCLESCore 15 C State Transition CyclesUNC_P_CORE16_TRANSITION_CYCLESCore 16 C State Transition CyclesUNC_P_CORE17_TRANSITION_CYCLESCore 17 C State Transition CyclesPackage C State residency - C0UNC_P_PKG_RESIDENCY_C1E_CYCLESPackage C State residency - C1EUNC_P_PKG_RESIDENCY_C2E_CYCLESPackage C State residency - C2EPackage C State residency - C3Package C State residency - C6Package C State residency - C7[UNC_UBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
[UNC_R2PCIE=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
Intel Haswell-EP R2PCIe uncoreAD counter clockwise Egress queueBL counter clockwise Egress queueAK counter clockwise Egress queueClockwise with any polarity on virtual ringCounter-clockwise with any polarity on virtual ringany direction and any polarity on virtual ringCounter-clockwise and even ring polarity on virtual ringCounter-clockwise and odd ring polarity on virtual ringClockwise and even ring polarity on virtual ringClockwise and odd ring polarity on virtual ring[UNC_R3QPI=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
Intel Haswell-EP R3QPI2 uncoreIntel Haswell-EP R3QPI1 uncoreIntel Haswell-EP R3QPI0 uncoreVN1 Ingress Occupancy AccumulatorReads (not including prefetches)Track request coming from port designated in IRP OrderingQ filterHit in Exclusive or Shared stateSlow transfer of I-state cachelineSlow transfer of S-state cachelineSlow transfer of e-state cachelineSlow transfer of M-state cachelineCache insert of read transaction as secondaryCache insert of write transaction as secondaryCache insert of atomic transaction as secondaryFastpath trasnfers from primary to secondaryPrefetch ack hints from primary to secondary[UNC_SBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
Intel Haswell-EP S-BOX3 uncoreIntel Haswell-EP S-BOX2 uncoreIntel Haswell-EP S-BOX1 uncoreIntel Haswell-EP S-BOX0 uncoreIntel BroadwellX C-Box 23 uncoreIntel BroadwellX C-Box 22 uncoreIntel BroadwellX C-Box 21 uncoreIntel BroadwellX C-Box 20 uncoreIntel BroadwellX C-Box 19 uncoreIntel BroadwellX C-Box 18 uncoreIntel BroadwellX C-Box 17 uncoreIntel BroadwellX C-Box 16 uncoreIntel BroadwellX C-Box 15 uncoreIntel BroadwellX C-Box 14 uncoreIntel BroadwellX C-Box 13 uncoreIntel BroadwellX C-Box 12 uncoreIntel BroadwellX C-Box 11 uncoreIntel BroadwellX C-Box 10 uncoreIntel BroadwellX C-Box 9 uncoreIntel BroadwellX C-Box 8 uncoreIntel BroadwellX C-Box 7 uncoreIntel BroadwellX C-Box 6 uncoreIntel BroadwellX C-Box 5 uncoreIntel BroadwellX C-Box 4 uncoreIntel BroadwellX C-Box 3 uncoreIntel BroadwellX C-Box 2 uncoreIntel BroadwellX C-Box 1 uncoreIntel BroadwellX C-Box 0 uncoreSince occupancy counts can only be captured in the Cbos 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect.  E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.Counts the number of cycles either the local distress or incoming distress signals are asserted.  Incoming distress includes both up and dn.Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.  CBoGlCtrl[22:18] bits correspond to [FMESI] state.Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.Miscellaneous events in the Cbo.Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.Counts number of allocations per cycle into the specified Ingress queue.Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.Counts number of entries in the specified Ingress queue in each cycle.Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  There are a number of subevent filters but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.  There are a number of subevent filters but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.Egress Allocations -- AD - CacheboEgress Allocations -- AD - CoreboEgress Allocations -- AK - CacheboEgress Allocations -- AK - CoreboEgress Allocations -- BL - CachenoEgress Allocations -- BL - CoreboEgress Allocations -- IV - CacheboMisses to Local Memory - Opcode MatchedMisses to Remote Memory - Opcode MatchedRemote Memory - Opcode MatchedSBo Credits Occupancy -- For AD RingSBo Credits Occupancy -- For BL RingSBo Credits Acquired -- For AD RingSBo Credits Acquired -- For BL RingIngress Occupancy -- IRQ RejectedIngress Occupancy -- PRQ RejectsISMQ Request Queue Rejects -- No AD Sbo CreditsISMQ Request Queue Rejects -- No BL Sbo CreditsISMQ Request Queue Rejects -- Target Node FilterISMQ Retries -- No Egress CreditsISMQ Retries -- No IIO CreditsISMQ Retries -- No QPI CreditsIngress Request Queue Rejects -- No AD Sbo CreditsIngress Request Queue Rejects -- No BL Sbo CreditsIngress Request Queue Rejects -- Target Node FilterIngress Request Queue Rejects -- Address ConflictIngress Request Queue Rejects -- Any RejectIngress Request Queue Rejects -- No Egress CreditsIngress Request Queue Rejects -- No IIO CreditsIngress Request Queue Rejects -- Ingress Request Queue Rejects -- No QPI CreditsIngress Request Queue Rejects -- No RTIDsProbe Queue Retries -- No AD Sbo CreditsProbe Queue Retries -- Target Node FilterProbe Queue Retries -- Address ConflictProbe Queue Retries -- Any RejectProbe Queue Retries -- No Egress CreditsProbe Queue Retries -- No QPI CreditsIngress Allocations -- IRQ RejectedIngress Arbiter Blocking Cycles -- IRQIngress Arbiter Blocking Cycles -- IPQIngress Arbiter Blocking Cycles -- ISMQ_BIDIngress Arbiter Blocking Cycles -- PRQNumber of LLC responses that bounced on the Ring. -- ADNumber of LLC responses that bounced on the Ring. -- AKNumber of LLC responses that bounced on the Ring. -- BLNumber of LLC responses that bounced on the Ring. -- Snoops of processors cachee.BL Ring in Use -- Down and EvenBL Ring in Use -- Down and OddAK Ring In Use -- Down and EvenAK Ring In Use -- Down and OddAD Ring In Use -- Down and EvenAD Ring In Use -- Down and OddCbo Misc -- DRd hitting non-M with raw CV=0Cbo Misc -- Clean Victim with raw CV=0Cbo Misc -- Silent Snoop EvictionCbo Misc -- Write Combining AliasingLines Victimized -- Victimized Lines that Match NIDCache Lookups -- Data Read RequestCache Lookups -- Lookups that Match NIDCache Lookups -- Any Read RequestCache Lookups -- External Snoop RequestCache Lookups -- Write RequestsVirtual Logical Wire (legacy) message were received from uncorePHOLD cycles.  Filter from source CoreID.Number outstanding register requests within message channel trackerCycles PHOLD Assert to Ack. Assert to ACKIntel BroadwellX S-BOX3 uncoreIntel BroadwellX S-BOX2 uncoreIntel BroadwellX S-BOX1 uncoreIntel BroadwellX S-BOX0 uncoreCounts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  There is only 1 IV ring in BDX.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.Egress Occupancy -- AD - BouncesEgress Occupancy -- AD - CreditsEgress Occupancy -- BL - BouncesEgress Occupancy -- BL - CreditsEgress Allocations -- AD - BouncesEgress Allocations -- AD - CreditsEgress Allocations -- BL - BouncesEgress Allocations -- BL - CreditsIngress Occupancy -- AD - BouncesIngress Occupancy -- AD - CreditsIngress Occupancy -- BL - BouncesIngress Occupancy -- BL - CreditsIngress Allocations -- AD - BouncesIngress Allocations -- AD - CreditsIngress Allocations -- BL - BouncesIngress Allocations -- BL - CreditsNumber of LLC responses that bounced on the Ring. -- Number of LLC responses that bounced on the Ring. -- Acknowledgements to coreNumber of LLC responses that bounced on the Ring. -- Data Responses to coreCycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.Accumulates the occupancy of te HA BT pool in every cycle. This can be used with the 'not empty' stat to calculate the average queue occupancy or the 'allocations' stat to calculate average queue latency. HA BTs are allocated as son as a request enters the HA and are released after the snoop response and data return and the response is returned to the ringCounts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.Number of Direct2Core messages sentNumber of cycles in which Direct2Core was disabledNumber of Reads where Direct2Core overriddenDirectory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data returnCounts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMCs RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given iven time.Number of Sbo 0 credits acquired in a given cycle, per ring.Number of Sbo 0 credits in use in a given cycle, per ring.Number of Sbo 1 credits acquired in a given cycle, per ring.Number of Sbo 1 credits in use in a given cycle, per ring.Counts the number of reads when the snoop was on the critical path to the data return.Counts cycles when one or more snoops are outstanding.Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.  In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.Number of snoop responses received for a Local requestNumber of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the rhe ring.Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system cant schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requestss.Counts the number of DRS messages sent out on the BL ring.  This can be filtered by the destination.Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMCs WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given iven time.HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 0HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 1HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 2HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 3Injection Starvation -- For AK RingInjection Starvation -- For BL RingOutbound DRS Ring Transactions to Cache -- Data to CacheOutbound DRS Ring Transactions to Cache -- Data to CoreOutbound DRS Ring Transactions to Cache -- Data to QPIData Pending Occupancy Accumultor -- Local RequestsData Pending Occupancy Accumultor -- Remote RequestsTracker Occupancy Accumultor -- Local InvItoE RequestsTracker Occupancy Accumultor -- Remote InvItoE RequestsTracker Occupancy Accumultor -- Local Read RequestsTracker Occupancy Accumultor -- Remote Read RequestsTracker Occupancy Accumultor -- Local Write RequestsTracker Occupancy Accumultor -- Remote Write RequestsTracker Cycles Not Empty -- All RequestsTracker Cycles Not Empty -- Local RequestsTracker Cycles Not Empty -- Remote RequestsTracker Cycles Full -- Cycles Completely UsedTracker Cycles Full -- Cycles GP Completely UsedHA Requests to a TAD Region - Group 1 -- TAD Region 10HA Requests to a TAD Region - Group 1 -- TAD Region 11HA Requests to a TAD Region - Group 1 -- TAD Region 8HA Requests to a TAD Region - Group 1 -- TAD Region 9HA Requests to a TAD Region - Group 0 -- TAD Region 0HA Requests to a TAD Region - Group 0 -- TAD Region 1HA Requests to a TAD Region - Group 0 -- TAD Region 2HA Requests to a TAD Region - Group 0 -- TAD Region 3HA Requests to a TAD Region - Group 0 -- TAD Region 4HA Requests to a TAD Region - Group 0 -- TAD Region 5HA Requests to a TAD Region - Group 0 -- TAD Region 6HA Requests to a TAD Region - Group 0 -- TAD Region 7Stall on No Sbo Credits -- For SBo0, AD RingStall on No Sbo Credits -- For SBo0, BL RingStall on No Sbo Credits -- For SBo1, AD RingStall on No Sbo Credits -- For SBo1, BL RingSnoop Responses Received Local -- OtherSnoop Responses Received Local -- RspCnflctSnoop Responses Received Local -- RspISnoop Responses Received Local -- RspIFwdSnoop Responses Received Local -- RspSSnoop Responses Received Local -- RspSFwdSnoop Responses Received Local -- Rsp*FWD*WBSnoop Responses Received Local -- Rsp*WBSnoop Responses Received -- RSPCNFLCT*Snoop Responses Received -- RspISnoop Responses Received -- RspIFwdSnoop Responses Received -- RspSSnoop Responses Received -- RspSFwdSnoop Responses Received -- Rsp*Fwd*WBSnoop Responses Received -- Rsp*WBTracker Snoops Outstanding Accumulator -- Local RequestsTracker Snoops Outstanding Accumulator -- Remote RequestsCycles with Snoops Outstanding -- All RequestsCycles with Snoops Outstanding -- Local RequestsCycles with Snoops Outstanding -- Remote RequestsData beat the Snoop Responses -- Local RequestsData beat the Snoop Responses -- Remote RequestsiMC RPQ Credits Empty - Regular -- Channel 0iMC RPQ Credits Empty - Regular -- Channel 1iMC RPQ Credits Empty - Regular -- Channel 2iMC RPQ Credits Empty - Regular -- Channel 3Read and Write Requests -- Local InvItoEsRead and Write Requests -- Remote InvItoEsRead and Write Requests -- ReadsRead and Write Requests -- Local ReadsRead and Write Requests -- Remote ReadsRead and Write Requests -- WritesRead and Write Requests -- Local WritesRead and Write Requests -- Remote WritesOSB Early Data Return -- Reads to Local  IOSB Early Data Return -- Reads to Local SOSB Early Data Return -- Reads to Remote IOSB Early Data Return -- Reads to Remote SOSB Snoop Broadcast -- CancelledOSB Snoop Broadcast -- Local InvItoEOSB Snoop Broadcast -- Local ReadsOSB Snoop Broadcast -- Reads Local -  UsefulOSB Snoop Broadcast -- Remote - UsefulHA to iMC Full Line Writes Issued -- All WritesHA to iMC Full Line Writes Issued -- Full Line Non-ISOCHHA to iMC Full Line Writes Issued -- ISOCH Full LineHA to iMC Full Line Writes Issued -- Partial Non-ISOCHHA to iMC Full Line Writes Issued -- ISOCH PartialHA to iMC Normal Priority Reads Issued -- Normal PriorityCycles without QPI Ingress Credits -- AD to QPI Link 0Cycles without QPI Ingress Credits -- AD to QPI Link 1Cycles without QPI Ingress Credits -- BL to QPI Link 0Cycles without QPI Ingress Credits -- BL to QPI Link 1Counts Number of times HitMe Cache is accessed -- op is AckCnfltWbICounts Number of times HitMe Cache is accessed -- All RequestsCounts Number of times HitMe Cache is accessed -- AllocationsCounts Number of times HitMe Cache is accessed -- HOM RequestsCounts Number of times HitMe Cache is accessed -- InvalidationsCounts Number of times HitMe Cache is accessed -- op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoECounts Number of times HitMe Cache is accessed -- op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbICounts Number of times HitMe Cache is accessed -- op is RspIFwd or RspIFwdWb for a local requestCounts Number of times HitMe Cache is accessed -- op is RspIFwd or RspIFwdWb for a remote requestCounts Number of times HitMe Cache is accessed -- op is RsSFwd or RspSFwdWbCounts Number of times HitMe Cache is accessed -- op is WbMtoE or WbMtoSCounts Number of times HitMe Cache is accessed -- op is WbMtoIAccumulates Number of PV bits set on HitMe Cache Hits -- op is AckCnfltWbIAccumulates Number of PV bits set on HitMe Cache Hits -- All RequestsAccumulates Number of PV bits set on HitMe Cache Hits -- HOM RequestsAccumulates Number of PV bits set on HitMe Cache Hits -- op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoEAccumulates Number of PV bits set on HitMe Cache Hits -- op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbIAccumulates Number of PV bits set on HitMe Cache Hits -- op is RspIFwd or RspIFwdWb for a local requestAccumulates Number of PV bits set on HitMe Cache Hits -- op is RspIFwd or RspIFwdWb for a remote requestAccumulates Number of PV bits set on HitMe Cache Hits -- op is RsSFwd or RspSFwdWbAccumulates Number of PV bits set on HitMe Cache Hits -- op is WbMtoE or WbMtoSAccumulates Number of PV bits set on HitMe Cache Hits -- op is WbMtoICounts Number of Hits in HitMe Cache -- op is AckCnfltWbICounts Number of Hits in HitMe Cache -- All RequestsCounts Number of Hits in HitMe Cache -- AllocationsCounts Number of Hits in HitMe Cache -- HOM RequestsCounts Number of Hits in HitMe Cache -- InvalidationsCounts Number of Hits in HitMe Cache -- op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoECounts Number of Hits in HitMe Cache -- op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbICounts Number of Hits in HitMe Cache -- op is RspIFwd or RspIFwdWb for a local requestCounts Number of Hits in HitMe Cache -- op is RspIFwd or RspIFwdWb for a remote requestCounts Number of Hits in HitMe Cache -- op is RsSFwd or RspSFwdWbCounts Number of Hits in HitMe Cache -- op is WbMtoE or WbMtoSCounts Number of Hits in HitMe Cache -- op is WbMtoIDirectory Updates -- Any Directory UpdateDirectory Updates -- Directory ClearDirectory Updates -- Directory SetDirectory Lookups -- Snoop Not NeededDirectory Lookups -- Snoop NeededCounts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.DRAM RD_CAS and WR_CAS CommandsCounts the number of times that the precharge all command was sent.Counts the number of refreshes issued.Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.  Major modes are channel-wide, and not a per-rank (or dimm or bank) mode.Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.Counts the number of DRAM Precharge commands sent on this channel.Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencieies.Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.Transition from WMM to RMM because of low threshold -- Transition from WMM to RMM because of starve counterTransition from WMM to RMM because of low threshold -- VMSE WR PUSH issued -- VMSE write PUSH issued in RMMVMSE WR PUSH issued -- VMSE write PUSH issued in WMMRD_CAS Access to Rank 2 -- Bank 0Access to Rank 0 -- Bank Group 0 (Banks 0-3)Access to Rank 0 -- Bank Group 1 (Banks 4-7)Access to Rank 0 -- Bank Group 2 (Banks 8-11)Access to Rank 0 -- Bank Group 3 (Banks 12-15)Read CAS issued with HIGH priorityRead CAS issued with LOW priorityRead CAS issued with MEDIUM priorityRead CAS issued with PANIC NON ISOCH priority (starved)DRAM Precharge commands. -- Precharge due to bypassDRAM Precharge commands. -- Precharge due to timer expirationDRAM Precharge commands. -- Precharges due to page missDRAM Precharge commands. -- Precharge due to readDRAM Precharge commands. -- Precharge due to writeRead Preemption Count -- Read over Read PreemptionRead Preemption Count -- Read over Write PreemptionCycles in a Major Mode -- Isoch Major ModeCycles in a Major Mode -- Partial Major ModeCycles in a Major Mode -- Read Major ModeCycles in a Major Mode -- Write Major ModeDRAM RD_CAS and WR_CAS Commands. All DRAM WR_CAS (w/ and w/out auto-pre)DRAM RD_CAS and WR_CAS Commands. All DRAM Reads (RD_CAS + Underfills)DRAM RD_CAS and WR_CAS Commands. All DRAM RD_CAS (w/ and w/out auto-pre)DRAM RD_CAS and WR_CAS Commands. Read CAS issued in RMMDRAM RD_CAS and WR_CAS Commands. Underfill Read IssuedDRAM RD_CAS and WR_CAS Commands. Read CAS issued in WMMDRAM RD_CAS and WR_CAS Commands. All DRAM WR_CAS (both Modes)DRAM RD_CAS and WR_CAS Commands. DRAM WR_CAS (w/ and w/out auto-pre) in Read Major ModeDRAM RD_CAS and WR_CAS Commands. DRAM WR_CAS (w/ and w/out auto-pre) in Write Major ModeDRAM Activate Count -- Activate due to WriteDRAM Activate Count -- Activate due to ReadAccumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.Counts the number of coherency related operations servied by the IRPCounts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portItID.Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.Counts the number of requests issued to the switch (towards the devices).Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.Inbound Transaction Count -- AtomicInbound Transaction Count -- Select Source via IRP orderingQ registerInbound Transaction Count -- OtherInbound Transaction Count -- Read PrefetchesInbound Transaction Count -- ReadsInbound Transaction Count -- WritesInbound Transaction Count -- Write PrefetchesMisc Events - Set 1 -- Data ThrottledMisc Events - Set 1 -- Received InvalidMisc Events - Set 1 -- Received ValidMisc Events - Set 1 -- Slow Transfer of I LineMisc Events - Set 1 -- Slow Transfer of S LineMisc Events - Set 1 -- Slow Transfer of E LineMisc Events - Set 1 -- Slow Transfer of M LineMisc Events - Set 0 -- Cache Inserts of Atomic Transactions as SecondaryMisc Events - Set 0 -- Cache Inserts of Read Transactions as SecondaryMisc Events - Set 0 -- Cache Inserts of Write Transactions as SecondaryMisc Events - Set 0 -- Fastpath RejectsMisc Events - Set 0 -- Fastpath RequestsMisc Events - Set 0 -- Fastpath Transfers From Primary to SecondaryMisc Events - Set 0 -- Prefetch Ack Hints From Primary to SecondaryMisc Events - Set 0 -- Prefetch TimeOutTotal Write Cache Occupancy -- Any SourceTotal Write Cache Occupancy -- Select SourceThe PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controllers dclk, counts at a constant rate making it a good measure of actual wall timee.Number of cycles spent performing core C state transitions.  There is one event per core.Counts the number of times when a configurable cores had a C-state demotionCounts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.Counts the number of cycles when the OS is the upper limit on frequency.Counts the number of cycles when power is the upper limit on frequency.Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.Counts the number of cycles that we are in internal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.Number of cycles spent performing core C state transitions across all cores.Ring GV down due to low trafficUNC_P_UFS_TRANSITIONS_IO_P_LIMITUNC_P_UFS_TRANSITIONS_NO_CHANGERing GV with same final and initial frequencyRing GV up due to high ring trafficUNC_P_UFS_TRANSITIONS_UP_STALLRing GV up due to high core stallsCycles spent in phase-shedding power state 0Cycles spent in phase-shedding power state 1Cycles spent in phase-shedding power state 2Cycles spent in phase-shedding power state 3Number of cores in C-State -- C0 and C1Number of cores in C-State -- C3Number of cores in C-State -- C6 and C7Counts the number of clocks in the QPI LL.  This clock runs at 1/4th the GT/s speed of the QPI link.  For example, a 4GT/s link will have qfclk or 1GHz.  BDX does not support dynamic link speeds, so this frequency is fixexed.Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.Number of QPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a QPI link.  Use edge detect to count the number of instances when the QPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.Counts the number of flits received from the QPI Link.Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).  In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).  In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).  In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).  In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.Number of allocations into the QPI Tx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO fro Snoop messages on AD.Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.Number of VNA credits returned.Number of VNA credits in the Rx side that are waitng to be returned back across the link.R3QPI Egress Credit Occupancy - DRS -- for VN0R3QPI Egress Credit Occupancy - DRS -- for VN1R3QPI Egress Credit Occupancy - DRS -- for Shared VNFlits Transferred - Group 2 -- Non-Coherent Bypass Tx FlitsFlits Transferred - Group 2 -- Non-Coherent data Tx FlitsFlits Transferred - Group 2 -- Non-Coherent non-data Tx FlitsFlits Transferred - Group 2 -- Non-Coherent standard Tx FlitsFlits Transferred - Group 2 -- Non-Data Response Tx Flits - ADFlits Transferred - Group 2 -- Non-Data Response Tx Flits - AKFlits Transferred - Group 1 -- DRS Flits (both Header and Data)Flits Transferred - Group 1 -- DRS Data FlitsFlits Transferred - Group 1 -- DRS Header FlitsFlits Transferred - Group 1 -- HOM FlitsFlits Transferred - Group 1 -- HOM Non-Request FlitsFlits Transferred - Group 1 -- HOM Request FlitsFlits Transferred - Group 1 -- SNP FlitsFlits Transferred - Group 0 -- Data Tx FlitsFlits Transferred - Group 0 -- Non-Data protocol Tx FlitsNumber of data flits over QPI that do not hold payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits acrossFlits Received - Group 2 -- Non-Coherent Rx FlitsFlits Received - Group 2 -- Non-Coherent data Rx FlitsFlits Received - Group 2 -- Non-Coherent non-data Rx FlitsFlits Received - Group 2 -- Non-Coherent standard Rx FlitsFlits Received - Group 2 -- Non-Data Response Rx Flits - ADFlits Received - Group 2 -- Non-Data Response Rx Flits - AKFlits Received - Group 1 -- DRS Flits (both Header and Data)Flits Received - Group 1 -- DRS Data FlitsFlits Received - Group 1 -- DRS Header FlitsFlits Received - Group 1 -- HOM FlitsFlits Received - Group 1 -- HOM Non-Request FlitsFlits Received - Group 1 -- HOM Request FlitsFlits Received - Group 1 -- SNP FlitsDirect 2 Core Spawning -- Spawn Failure - Egress CreditsDirect 2 Core Spawning -- Spawn Failure - Egress and RBT MissDirect 2 Core Spawning -- Spawn Failure - Egress and RBT InvalidDirect 2 Core Spawning -- Spawn Failure - Egress and RBT Miss, InvalidDirect 2 Core Spawning -- Spawn Failure - RBT MissDirect 2 Core Spawning -- Spawn Failure - RBT InvalidDirect 2 Core Spawning -- Spawn Failure - RBT Miss and InvalidDirect 2 Core Spawning -- Spawn SuccessIntel BroadwellX R2PCIe uncoreCounts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.Counts the number of times when a request destined for the AK ingress bounced.Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.Counts the number of cycles when the R2PCIe Egress buffer is full.Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.SBo0 Credits Acquired -- For AD RingSBo0 Credits Acquired -- For BL RingIngress Occupancy Accumulator -- DRSIntel BroadwellX R3QPI2 uncoreIntel BroadwellX R3QPI1 uncoreIntel BroadwellX R3QPI0 uncoreCounts the number of uclks in the QPI uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.No credits available to send to Cbox on the AD Ring (covers higher CBoxes)No credits available to send to Cbox on the AD Ring (covers lower CBoxes)No credits available to send to either HA or R2 on the BL RingNo credits available to send to QPI0 on the AD RingNo credits available to send to QPI0 on the BL RingNo credits available to send to QPI1 on the AD RingNo credits available to send to QPI1 on the BL RingNumber of cycles the ringstop is in starvation (per ring)Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transferred).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transferred in a given message class using an qfclk event.Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.VNA Credit Reject -- DRS Message ClassVNA Credit Reject -- HOM Message ClassVNA Credit Reject -- NCB Message ClassVNA Credit Reject -- NCS Message ClassVNA Credit Reject -- NDR Message ClassVNA Credit Reject -- SNP Message ClassVNA credit Acquisitions -- HOM Message ClassVN1 Credit Used -- DRS Message ClassVN1 Credit Used -- HOM Message ClassVN1 Credit Used -- NCB Message ClassVN1 Credit Used -- NCS Message ClassVN1 Credit Used -- NDR Message ClassVN1 Credit Used -- SNP Message ClassVN1 Credit Acquisition Failed on DRS -- DRS Message ClassVN1 Credit Acquisition Failed on DRS -- HOM Message ClassVN1 Credit Acquisition Failed on DRS -- NCB Message ClassVN1 Credit Acquisition Failed on DRS -- NCS Message ClassVN1 Credit Acquisition Failed on DRS -- NDR Message ClassVN1 Credit Acquisition Failed on DRS -- SNP Message ClassVN0 Credit Used -- DRS Message ClassVN0 Credit Used -- HOM Message ClassVN0 Credit Used -- NCB Message ClassVN0 Credit Used -- NCS Message ClassVN0 Credit Used -- NDR Message ClassVN0 Credit Used -- SNP Message ClassVN0 Credit Acquisition Failed on DRS -- DRS Message ClassVN0 Credit Acquisition Failed on DRS -- HOM Message ClassVN0 Credit Acquisition Failed on DRS -- NCB Message ClassVN0 Credit Acquisition Failed on DRS -- NCS Message ClassVN0 Credit Acquisition Failed on DRS -- NDR Message ClassVN0 Credit Acquisition Failed on DRS -- SNP Message ClassSBo1 Credits Acquired -- For AD RingSBo1 Credits Acquired -- For BL RingVN1 Ingress Cycles Not Empty -- DRSVN1 Ingress Cycles Not Empty -- HOMVN1 Ingress Cycles Not Empty -- NCBVN1 Ingress Cycles Not Empty -- NCSVN1 Ingress Cycles Not Empty -- NDRVN1 Ingress Cycles Not Empty -- SNPIngress Cycles Not Empty -- HOMIngress Cycles Not Empty -- NDRIngress Cycles Not Empty -- SNP[UNC_CHA=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d tid_en=%d] %s
[UNC_CHA_FILTER0=0x%lx thread_id=%d source=0x%x state=0x%x]
[UNC_CHA_FILTER1=0x%lx rem=%d loc=%d all_opc=%d nm=%d not_nm=%d opc0=0x%x opc1=0x%x nc=%d isoc=%d]
Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.Number of CMS Agent 0 AD credits in use in a given cycle, per transgressNumber of CMS Agent 0 BL credits acquired in a given cycle, per transgress.Number of CMS Agent 0 BL credits in use in a given cycle, per transgressNumber of CMS Agent 1 AD credits acquired in a given cycle, per transgress.Number of CMS Agent 1 AD credits in use in a given cycle, per transgressNumber of CMS Agent 1 BL credits in use in a given cycle, per transgressNumber of CMS Agent 1 BL credits acquired in a given cycle, per transgress.Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).Since occupancy counts can only be captured in the Cbos 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.  The filtering available is found in the control register - threshold, invert and edge detect.  E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.Counts the number of transactions that looked up the Home Agent directory.  Can be filtered by requests that had to snoop and those that did not have to.Counts the number of directory updates that were required.  These result in writes to the memory controller.Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirementsCounts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.  CHAFilter0[24:21,17] bits correspond to [FMESI] state.Miscellaneous events in the CHA.Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMCs AD Ingress queuee.Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMSMQ)Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priorityNumber of packets bypassing the CMS IngressCounts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the meshOccupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the meshCounts the number of snoops issued by the HA.Number of snoop responses received for a Local  requestUNC_C_STALL_NO_TXR_HORZ_CRD_AD_AG0Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_C_STALL_NO_TXR_HORZ_CRD_AD_AG1Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_C_STALL_NO_TXR_HORZ_CRD_BL_AG0Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_C_STALL_NO_TXR_HORZ_CRD_BL_AG1Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.Counts number of Egress packets NACKed on to the Horizontal RinngOccupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.Counts number of Egress packets NACKed on to the Vertical RinngOccupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.Counts the number of times when the CHA was received WbPushMtoICounts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMCs BL Ingress queuee.Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.Core Cross Snoop Responses -- Any RspIFwdFECore Cross Snoop Responses -- Any RspSFwdFECore Cross Snoop Responses -- Any RspSFwdMCore Cross Snoop Responses -- Any RspHitFSECore Cross Snoop Responses -- Core RspIFwdFECore Cross Snoop Responses -- Core RspIFwdMCore Cross Snoop Responses -- Core RspSFwdFECore Cross Snoop Responses -- Core RspSFwdMCore Cross Snoop Responses -- Core RspHitFSECore Cross Snoop Responses -- Evict RspIFwdFECore Cross Snoop Responses -- Evict RspIFwdMCore Cross Snoop Responses -- Evict RspSFwdFECore Cross Snoop Responses -- Evict RspSFwdMCore Cross Snoop Responses -- Evict RspHitFSECore Cross Snoop Responses -- External RspIFwdFECore Cross Snoop Responses -- External RspIFwdMCore Cross Snoop Responses -- External RspSFwdFECore Cross Snoop Responses -- External RspSFwdMCore Cross Snoop Responses -- External RspHitFSECHA iMC CHNx WRITE Credits Empty -- EDC0_SMI2CHA iMC CHNx WRITE Credits Empty -- EDC1_SMI3CHA iMC CHNx WRITE Credits Empty -- EDC2_SMI4CHA iMC CHNx WRITE Credits Empty -- EDC3_SMI5CHA iMC CHNx WRITE Credits Empty -- MC0_SMI0CHA iMC CHNx WRITE Credits Empty -- MC1_SMI1WbPushMtoI -- Pushed to MemoryVertical IV Ring in Use -- DownVertical BL Ring in Use -- Down and EvenVertical BL Ring in Use -- Down and OddVertical BL Ring in Use -- Up and EvenVertical BL Ring in Use -- Up and OddVertical AK Ring In Use -- Down and EvenVertical AK Ring In Use -- Down and OddVertical AK Ring In Use -- Up and EvenVertical AK Ring In Use -- Up and OddVertical AD Ring In Use -- Down and EvenVertical AD Ring In Use -- Down and OddVertical AD Ring In Use -- Up and EvenVertical AD Ring In Use -- Up and OddCMS Vertical Egress Injection Starvation -- AD - Agent 0CMS Vertical Egress Injection Starvation -- AD - Agent 1CMS Vertical Egress Injection Starvation -- AK - Agent 0CMS Vertical Egress Injection Starvation -- AK - Agent 1CMS Vertical Egress Injection Starvation -- BL - Agent 0CMS Vertical Egress Injection Starvation -- BL - Agent 1CMS Vertical Egress Injection Starvation -- IVCMS Vert Egress Occupancy -- AD - Agent 0CMS Vert Egress Occupancy -- AD - Agent 1CMS Vert Egress Occupancy -- AK - Agent 0CMS Vert Egress Occupancy -- AK - Agent 1CMS Vert Egress Occupancy -- BL - Agent 0CMS Vert Egress Occupancy -- BL - Agent 1CMS Vert Egress Occupancy -- IVCMS Vertical Egress NACKs -- AD - Agent 0CMS Vertical Egress NACKs -- AD - Agent 1CMS Vertical Egress NACKs -- AK - Agent 0CMS Vertical Egress NACKs -- AK - Agent 1CMS Vertical Egress NACKs -- BL - Agent 0CMS Vertical Egress NACKs -- BL - Agent 1CMS Vertical Egress NACKs -- IVCMS Vert Egress Allocations -- AD - Agent 0CMS Vert Egress Allocations -- AD - Agent 1CMS Vert Egress Allocations -- AK - Agent 0CMS Vert Egress Allocations -- AK - Agent 1CMS Vert Egress Allocations -- BL - Agent 0CMS Vert Egress Allocations -- BL - Agent 1CMS Vert Egress Allocations -- IVCycles CMS Vertical Egress Queue Is Not Empty -- AD - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- AD - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- AK - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- AK - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- BL - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- BL - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- IVCycles CMS Vertical Egress Queue Is Full -- AD - Agent 0Cycles CMS Vertical Egress Queue Is Full -- AD - Agent 1Cycles CMS Vertical Egress Queue Is Full -- AK - Agent 0Cycles CMS Vertical Egress Queue Is Full -- AK - Agent 1Cycles CMS Vertical Egress Queue Is Full -- BL - Agent 0Cycles CMS Vertical Egress Queue Is Full -- BL - Agent 1Cycles CMS Vertical Egress Queue Is Full -- IVCMS Vertical ADS Used -- AD - Agent 0CMS Vertical ADS Used -- AD - Agent 1CMS Vertical ADS Used -- AK - Agent 0CMS Vertical ADS Used -- AK - Agent 1CMS Vertical ADS Used -- BL - Agent 0CMS Vertical ADS Used -- BL - Agent 1CMS Horizontal Egress Injection Starvation -- AD - BounceCMS Horizontal Egress Injection Starvation -- AK - BounceCMS Horizontal Egress Injection Starvation -- BL - BounceCMS Horizontal Egress Injection Starvation -- IV - BounceCMS Horizontal Egress Occupancy -- AD - BounceCMS Horizontal Egress Occupancy -- AD - CreditCMS Horizontal Egress Occupancy -- AK - BounceCMS Horizontal Egress Occupancy -- BL - BounceCMS Horizontal Egress Occupancy -- BL - CreditCMS Horizontal Egress Occupancy -- IV - BounceCMS Horizontal Egress NACKs -- AD - BounceCMS Horizontal Egress NACKs -- AD - CreditCMS Horizontal Egress NACKs -- AK - BounceCMS Horizontal Egress NACKs -- BL - BounceCMS Horizontal Egress NACKs -- BL - CreditCMS Horizontal Egress NACKs -- IV - BounceCMS Horizontal Egress Inserts -- AD - BounceCMS Horizontal Egress Inserts -- AD - CreditCMS Horizontal Egress Inserts -- AK - BounceCMS Horizontal Egress Inserts -- BL - BounceCMS Horizontal Egress Inserts -- BL - CreditCMS Horizontal Egress Inserts -- IV - BounceCycles CMS Horizontal Egress Queue is Not Empty -- AD - BounceCycles CMS Horizontal Egress Queue is Not Empty -- AD - CreditCycles CMS Horizontal Egress Queue is Not Empty -- AK - BounceCycles CMS Horizontal Egress Queue is Not Empty -- BL - BounceCycles CMS Horizontal Egress Queue is Not Empty -- BL - CreditCycles CMS Horizontal Egress Queue is Not Empty -- IV - BounceCycles CMS Horizontal Egress Queue is Full -- AD - BounceCycles CMS Horizontal Egress Queue is Full -- AD - CreditCycles CMS Horizontal Egress Queue is Full -- AK - BounceCycles CMS Horizontal Egress Queue is Full -- BL - BounceCycles CMS Horizontal Egress Queue is Full -- BL - CreditCycles CMS Horizontal Egress Queue is Full -- IV - BounceCMS Horizontal Bypass Used -- AD - BounceCMS Horizontal Bypass Used -- AD - CreditCMS Horizontal Bypass Used -- AK - BounceCMS Horizontal Bypass Used -- BL - BounceCMS Horizontal Bypass Used -- BL - CreditCMS Horizontal Bypass Used -- IV - BounceCMS Horizontal ADS Used -- AD - BounceCMS Horizontal ADS Used -- AD - CreditCMS Horizontal ADS Used -- AK - BounceCMS Horizontal ADS Used -- BL - BounceCMS Horizontal ADS Used -- BL - CreditTOR Occupancy -- All from LocalTOR Occupancy -- Hits from LocalTOR Occupancy -- Misses from LocalTOR Occupancy -- SF/LLC EvictionsTOR Occupancy -- Hit (Not a Miss)TOR Occupancy -- All from Local iATOR Occupancy -- Hits from Local iATOR Occupancy -- Misses from Local iATOR Occupancy -- All from Local IOTOR Occupancy -- Hits from Local IOTOR Occupancy -- Misses from Local IOIPQ Opcode: Snoop request to get uncacheable 'sanpshot' of dataIPQ Opcode: Snoop request to get cacheline intended to be cached in S-stateIPQ Opcode: Snoop request to get cacheline intended to be cached in E or S-stateIPQ Opcode: Snoop request to get cacheline intended to be cached in M, E or S-stateIPQ Opcode: Snoop invalidate own. To get cacheline in M or E-stateIPQ Opcode: Snoop invalidate. To get cacheline intended to be cached in E-stateIRQ Opcode: Demand data RFO (line to be cache in E state)IRQ Opcode: Demand data read (line to be cached in S or E states)IRQ Opcode: Partial reads 0-32 bytes uncacheable (IIO can be up to 64 bytes)IRQ Opcode: Full cacheline streaming storeIRQ Opcode: Partial streaming storeIRQ Opcode: Uncacheable Reads full cachelineIRQ Opcode: Write Invalidate Line (Partial)IRQ Opcode: Request writeback modified invalidate line, evict fill M-state line from coreIRQ Opcode: Request writeback modified set to exclusive (combine with any OPCODE umask)IRQ Opcode: Request clean E or F state lines writeback, ownership gone when writeback completesIRQ Opcode: Request clean E or F state lines writeback, core may retain ownership when writeback completesIRQ Opcode: Request invalidate line. Request exclusive ownership of the lineIRQ Opcode: LLC prefetch RFO, uncore first looks up the line in LLC. For a hit, the LRU is updated. For a miss, the RFO is initiatedIRQ Opcode: LLC prefetch code, uncore first looks up the line in LLC. For a hit, the LRU is updated. For a miss, the CRd is initiatedIRQ Opcode: LLC prefetch data, uncore first looks up the line in LLC. For a hit, the LRU is updated. For a miss, the DRd is initiatedIRQ Opcode: Interrupts logically addressedIRQ Opcode: Interrupts physically addressedIRQ Opcode: Interrupt priority updateIRQ Opcode: Request to start split lock sequenceIRQ Opcode: Request to start IDI lock sequencePRQ Opcode: Read current. Request cacheline in I-state. Used to obtain a coherent snapshot of an uncached linePRQ Opcode: Read code. Request cacheline in S-statePRQ Opcode: Read data. Request cacheline in E or S-statePRQ Opcode: Read data migratory. Request cacheline in E or S-state, except peer cache can forward cacheline in M-state without any writeback to memoryPRQ Opcode: Read invalidate own. Invalidate cacheline in M or E-statePRQ Opcode: Read invalidate X to I-statePRQ Opcode: Read invalidate I to E-statePRQ Opcode: Read invalidate. Request cacheline in E-state from home agentPRQ Opcode: Read invalidate I to M-stateTOR Inserts -- Hits from LocalTOR Inserts -- All from Local iA and IOTOR Inserts -- Misses from LocalTOR Inserts -- SF/LLC EvictionsTOR Inserts -- Hit (Not a Miss)TOR Inserts -- All from Local iATOR Inserts -- Hits from Local iATOR Inserts -- Misses from Local iATOR Inserts -- All from Local IOTOR Inserts -- Hits from Local IOTOR Inserts -- Misses from Local IOStall on No BL Agent1 Transgress Credits -- For Transgress 0Stall on No BL Agent1 Transgress Credits -- For Transgress 1Stall on No BL Agent1 Transgress Credits -- For Transgress 2Stall on No BL Agent1 Transgress Credits -- For Transgress 3Stall on No BL Agent1 Transgress Credits -- For Transgress 4Stall on No BL Agent1 Transgress Credits -- For Transgress 5Stall on No BL Agent0 Transgress Credits -- For Transgress 0Stall on No BL Agent0 Transgress Credits -- For Transgress 1Stall on No BL Agent0 Transgress Credits -- For Transgress 2Stall on No BL Agent0 Transgress Credits -- For Transgress 3Stall on No BL Agent0 Transgress Credits -- For Transgress 4Stall on No BL Agent0 Transgress Credits -- For Transgress 5Stall on No AD Agent1 Transgress Credits -- For Transgress 0Stall on No AD Agent1 Transgress Credits -- For Transgress 1Stall on No AD Agent1 Transgress Credits -- For Transgress 2Stall on No AD Agent1 Transgress Credits -- For Transgress 3Stall on No AD Agent1 Transgress Credits -- For Transgress 4Stall on No AD Agent1 Transgress Credits -- For Transgress 5Stall on No AD Agent0 Transgress Credits -- For Transgress 0Stall on No AD Agent0 Transgress Credits -- For Transgress 1Stall on No AD Agent0 Transgress Credits -- For Transgress 2Stall on No AD Agent0 Transgress Credits -- For Transgress 3Stall on No AD Agent0 Transgress Credits -- For Transgress 4Stall on No AD Agent0 Transgress Credits -- For Transgress 5Snoop Responses Received Local -- RspFwdSnoop Responses Received -- RspFwdSnoops Sent -- Broadcast snoop for Local RequestsSnoops Sent -- Broadcast snoops for Remote RequestsSnoops Sent -- Directed snoops for Local RequestsSnoops Sent -- Directed snoops for Remote RequestsSnoops Sent -- Broadcast or directed Snoops sent for Local RequestsSnoops Sent -- Broadcast or directed Snoops sent for Remote RequestsSnoop Filter Eviction -- E stateSnoop Filter Eviction -- M stateSnoop Filter Eviction -- S stateTransgress Ingress Occupancy -- AD - BounceTransgress Ingress Occupancy -- AD - CreditTransgress Ingress Occupancy -- AK - BounceTransgress Ingress Occupancy -- BL - BounceTransgress Ingress Occupancy -- BL - CreditTransgress Ingress Occupancy -- IV - BounceTransgress Ingress Allocations -- AD - BounceTransgress Ingress Allocations -- AD - CreditTransgress Ingress Allocations -- AK - BounceTransgress Ingress Allocations -- BL - BounceTransgress Ingress Allocations -- BL - CreditTransgress Ingress Allocations -- IV - BounceTransgress Injection Starvation -- AD - BounceTransgress Injection Starvation -- AD - CreditTransgress Injection Starvation -- AK - BounceTransgress Injection Starvation -- BL - BounceTransgress Injection Starvation -- BL - CreditTransgress Injection Starvation -- IFV - CreditTransgress Injection Starvation -- IV - BounceTransgress Ingress Bypass -- AD - BounceTransgress Ingress Bypass -- AD - CreditTransgress Ingress Bypass -- AK - BounceTransgress Ingress Bypass -- BL - BounceTransgress Ingress Bypass -- BL - CreditTransgress Ingress Bypass -- IV - BounceWBQ Rejects -- Merging these two together to make room for ANY_REJECT_*0WBQ Rejects -- Non UPI AK RequestWBQ Rejects -- Non UPI IV RequestRRQ Rejects -- Merging these two together to make room for ANY_REJECT_*0RRQ Rejects -- Non UPI AK RequestRRQ Rejects -- Non UPI IV RequestRequest Queue Retries -- Allow SnoopRequest Queue Retries -- Merging these two together to make room for ANY_REJECT_*0Request Queue Retries -- LLC VictimRequest Queue Retries -- PhyAddr MatchRequest Queue Retries -- SF VictimRequest Queue Retries -- VictimRequest Queue Retries -- AD REQ on VN0Request Queue Retries -- AD RSP on VN0Request Queue Retries -- Non UPI AK RequestRequest Queue Retries -- BL NCB on VN0Request Queue Retries -- BL NCS on VN0Request Queue Retries -- BL RSP on VN0Request Queue Retries -- BL WB on VN0Request Queue Retries -- Non UPI IV RequestIngress (from CMS) Request Queue Rejects -- Allow SnoopIngress (from CMS) Request Queue Rejects -- ANY0Ingress (from CMS) Request Queue Rejects -- HAIngress (from CMS) Request Queue Rejects -- LLC OR SF WayIngress (from CMS) Request Queue Rejects -- LLC VictimIngress (from CMS) Request Queue Rejects -- PhyAddr MatchIngress (from CMS) Request Queue Rejects -- SF VictimIngress (from CMS) Request Queue Rejects -- VictimIngress (from CMS) Request Queue Rejects -- AD REQ on VN0Ingress (from CMS) Request Queue Rejects -- AD RSP on VN0Ingress (from CMS) Request Queue Rejects -- Non UPI AK RequestIngress (from CMS) Request Queue Rejects -- BL NCB on VN0Ingress (from CMS) Request Queue Rejects -- BL NCS on VN0Ingress (from CMS) Request Queue Rejects -- BL RSP on VN0Ingress (from CMS) Request Queue Rejects -- BL WB on VN0Ingress (from CMS) Request Queue Rejects -- Non UPI IV RequestOther Retries -- Merging these two together to make room for ANY_REJECT_*0Other Retries -- PhyAddr MatchOther Retries -- AD REQ on VN0Other Retries -- AD RSP on VN0Other Retries -- Non UPI AK RequestOther Retries -- BL NCB on VN0Other Retries -- BL NCS on VN0Other Retries -- BL RSP on VN0Other Retries -- Non UPI IV RequestIngress (from CMS) Occupancy -- IPQIngress (from CMS) Occupancy -- IRQIngress (from CMS) Occupancy -- RRQIngress (from CMS) Occupancy -- WBQISMQ Retries -- Non UPI AK RequestISMQ Retries -- Non UPI IV RequestISMQ Rejects -- Non UPI AK RequestISMQ Rejects -- Non UPI IV RequestIngress (from CMS) Request Queue Rejects -- Merging these two together to make room for ANY_REJECT_*0Ingress Probe Queue Rejects -- Allow SnoopIngress Probe Queue Rejects -- ANY0Ingress Probe Queue Rejects -- HAIngress Probe Queue Rejects -- Merging these two together to make room for ANY_REJECT_*0Ingress Probe Queue Rejects -- LLC VictimIngress Probe Queue Rejects -- PhyAddr MatchIngress Probe Queue Rejects -- SF VictimIngress Probe Queue Rejects -- VictimIngress Probe Queue Rejects -- AD REQ on VN0Ingress Probe Queue Rejects -- AD RSP on VN0Ingress Probe Queue Rejects -- Non UPI AK RequestIngress Probe Queue Rejects -- BL NCB on VN0Ingress Probe Queue Rejects -- BL NCS on VN0Ingress Probe Queue Rejects -- BL RSP on VN0Ingress Probe Queue Rejects -- BL WB on VN0Ingress Probe Queue Rejects -- Non UPI IV RequestIngress (from CMS) Allocations -- IPQIngress (from CMS) Allocations -- IRQIngress (from CMS) Allocations -- IRQ RejectedIngress (from CMS) Allocations -- PRQIngress (from CMS) Allocations -- RRQIngress (from CMS) Allocations -- WBQSink Starvation on Vertical Ring -- ADSink Starvation on Vertical Ring -- Acknowledgements to coreSink Starvation on Vertical Ring -- Data Responses to coreSink Starvation on Vertical Ring -- Snoops of processors cachee.Sink Starvation on Horizontal Ring -- ADSink Starvation on Horizontal Ring -- AKSink Starvation on Horizontal Ring -- Acknowledgements to Agent 1Sink Starvation on Horizontal Ring -- BLSink Starvation on Horizontal Ring -- IVMessages that bounced on the Vertical Ring. -- ADMessages that bounced on the Vertical Ring. -- Acknowledgements to coreMessages that bounced on the Vertical Ring. -- Data Responses to coreMessages that bounced on the Vertical Ring. -- Snoops of processors cachee.Messages that bounced on the Horizontal Ring. -- ADMessages that bounced on the Horizontal Ring. -- AKMessages that bounced on the Horizontal Ring. -- BLMessages that bounced on the Horizontal Ring. -- IVRead and Write Requests -- InvalItoE LocalRead and Write Requests -- InvalItoE RemoteRead and Write Requests -- Reads LocalRead and Write Requests -- Reads RemoteRead and Write Requests -- Writes LocalRead and Write Requests -- Writes RemoteCHA iMC CHNx READ Credits Empty -- EDC0_SMI2CHA iMC CHNx READ Credits Empty -- EDC1_SMI3CHA iMC CHNx READ Credits Empty -- EDC2_SMI4CHA iMC CHNx READ Credits Empty -- EDC3_SMI5CHA iMC CHNx READ Credits Empty -- MC0_SMI0CHA iMC CHNx READ Credits Empty -- MC1_SMI1Cbo Misc -- CV0 Prefetch VictimLines Victimized -- Local - All LinesLines Victimized -- Local - Lines in E StateLines Victimized -- Local - Lines in F StateLines Victimized -- Local - Lines in M StateLines Victimized -- Local - Lines in S StateLines Victimized -- Remote - All LinesLines Victimized -- Remote - Lines in E StateLines Victimized -- Remote - Lines in F StateLines Victimized -- Remote - Lines in M StateLines Victimized -- Remote - Lines in S StateLines Victimized -- Lines in E StateLines Victimized -- Lines in F StateLines Victimized -- Lines in M StateLines Victimized -- Lines in S StateCache and Snoop Filter Lookups -- Any RequestCache and Snoop Filter Lookups -- Data Read RequestCache and Snoop Filter Lookups -- LocalCache and Snoop Filter Lookups -- RemoteCache and Snoop Filter Lookups -- External Snoop RequestCache and Snoop Filter Lookups -- Write RequestsCounts number of IODC deallocations -- IODC deallocated due to any reasonCounts number of IODC deallocations -- IODC deallocated due to conflicting transactionCounts number of IODC deallocations -- IODC deallocated due to WbMtoECounts number of IODC deallocations -- IODC deallocated due to WbMtoICounts number of IODC deallocations -- IODC deallocated due to WbPushMtoICounts Number of times IODC entry allocation is attempted -- Number of IODC allocationsCounts Number of times IODC entry allocation is attempted -- Number of IODC allocations dropped due to IODC FullCounts Number of times IODC entry allocation is attempted -- Number of IDOC allocation dropped due to OSB gateWrites Issued to the iMC by the HA -- Full Line Non-ISOCHWrites Issued to the iMC by the HA -- Full Line MIGWrites Issued to the iMC by the HA -- ISOCH Full LineWrites Issued to the iMC by the HA -- Partial Non-ISOCHWrites Issued to the iMC by the HA -- Partial MIGWrites Issued to the iMC by the HA -- ISOCH PartialHA to iMC Reads Issued -- NormalHA to iMC Reads Issued -- ISOCHHorizontal IV Ring in Use -- LeftHorizontal IV Ring in Use -- RightHorizontal BL Ring in Use -- Left and EvenHorizontal BL Ring in Use -- Left and OddHorizontal BL Ring in Use -- Right and EvenHorizontal BL Ring in Use -- Right and OddHorizontal AK Ring In Use -- Left and EvenHorizontal AK Ring In Use -- Left and OddHorizontal AK Ring In Use -- Right and EvenHorizontal AK Ring In Use -- Right and OddHorizontal AD Ring In Use -- Left and EvenHorizontal AD Ring In Use -- Left and OddHorizontal AD Ring In Use -- Right and EvenHorizontal AD Ring In Use -- Right and OddCounts the number of Allocate/Update to HitMe Cache -- Deallocate HtiME Reads without RspFwdI*Counts the number of Allocate/Update to HitMe Cache -- op is RspIFwd or RspIFwdWb for a local requestCounts the number of Allocate/Update to HitMe Cache -- Update HitMe Cache on RdInvOwn even if not RspFwdI*Counts the number of Allocate/Update to HitMe Cache -- op is RspIFwd or RspIFwdWb for a remote requestCounts the number of Allocate/Update to HitMe Cache -- Update HitMe Cache to SHARedCounts Number of Misses in HitMe Cache -- No SF/LLC HitS/F and op is RdInvOwnCounts Number of Misses in HitMe Cache -- op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*Counts Number of Misses in HitMe Cache -- SF/LLC HitS/F and op is RdInvOwnCounts Number of times HitMe Cache is accessed -- op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*Counts Number of times HitMe Cache is accessed -- op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoSCounts Number of Hits in HitMe Cache -- Exclusive hit and op is RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*Counts Number of Hits in HitMe Cache -- Shared hit and op is RdInvOwn, RdInv, Inv*Counts Number of Hits in HitMe Cache -- op is WbMtoECounts Number of Hits in HitMe Cache -- op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoSFaST wire asserted -- HorizontalFaST wire asserted -- VerticalEgress Blocking due to Ordering requirements -- DownEgress Blocking due to Ordering requirements -- UpDirectory Updates -- from HA pipeDirectory Updates -- from TOR pipeCore Cross Snoops Issued -- Any Cycle with Multiple SnoopsCore Cross Snoops Issued -- Any Single SnoopCore Cross Snoops Issued -- Any Snoop to Remote NodeCore Cross Snoops Issued -- Multiple Core RequestsCore Cross Snoops Issued -- Single Core RequestsCore Cross Snoops Issued -- Core Request to Remote NodeCore Cross Snoops Issued -- Multiple EvictionCore Cross Snoops Issued -- Single EvictionCore Cross Snoops Issued -- Eviction to Remote NodeCore Cross Snoops Issued -- Multiple External SnoopsCore Cross Snoops Issued -- Single External SnoopsCore Cross Snoops Issued -- External Snoop to Remote NodeCore PMA Events -- C1 TransitionCore PMA Events -- C6 TransitionCHA to iMC Bypass -- Intermediate bypass TakenCHA to iMC Bypass -- Not TakenCMS Agent1 BL Credits Acquired -- For Transgress 0CMS Agent1 BL Credits Acquired -- For Transgress 1CMS Agent1 BL Credits Acquired -- For Transgress 2CMS Agent1 BL Credits Acquired -- For Transgress 3CMS Agent1 BL Credits Acquired -- For Transgress 4CMS Agent1 BL Credits Acquired -- For Transgress 5CMS Agent1 BL Credits Occupancy -- For Transgress 0CMS Agent1 BL Credits Occupancy -- For Transgress 1CMS Agent1 BL Credits Occupancy -- For Transgress 2CMS Agent1 BL Credits Occupancy -- For Transgress 3CMS Agent1 BL Credits Occupancy -- For Transgress 4CMS Agent1 BL Credits Occupancy -- For Transgress 5CMS Agent1 AD Credits Occupancy -- For Transgress 0CMS Agent1 AD Credits Occupancy -- For Transgress 1CMS Agent1 AD Credits Occupancy -- For Transgress 2CMS Agent1 AD Credits Occupancy -- For Transgress 3CMS Agent1 AD Credits Occupancy -- For Transgress 4CMS Agent1 AD Credits Occupancy -- For Transgress 5CMS Agent1 AD Credits Acquired -- For Transgress 0CMS Agent1 AD Credits Acquired -- For Transgress 1CMS Agent1 AD Credits Acquired -- For Transgress 2CMS Agent1 AD Credits Acquired -- For Transgress 3CMS Agent1 AD Credits Acquired -- For Transgress 4CMS Agent1 AD Credits Acquired -- For Transgress 5CMS Agent0 BL Credits Occupancy -- For Transgress 0CMS Agent0 BL Credits Occupancy -- For Transgress 1CMS Agent0 BL Credits Occupancy -- For Transgress 2CMS Agent0 BL Credits Occupancy -- For Transgress 3CMS Agent0 BL Credits Occupancy -- For Transgress 4CMS Agent0 BL Credits Occupancy -- For Transgress 5CMS Agent0 BL Credits Acquired -- For Transgress 0CMS Agent0 BL Credits Acquired -- For Transgress 1CMS Agent0 BL Credits Acquired -- For Transgress 2CMS Agent0 BL Credits Acquired -- For Transgress 3CMS Agent0 BL Credits Acquired -- For Transgress 4CMS Agent0 BL Credits Acquired -- For Transgress 5CMS Agent0 AD Credits Occupancy -- For Transgress 0CMS Agent0 AD Credits Occupancy -- For Transgress 1CMS Agent0 AD Credits Occupancy -- For Transgress 2CMS Agent0 AD Credits Occupancy -- For Transgress 3CMS Agent0 AD Credits Occupancy -- For Transgress 4CMS Agent0 AD Credits Occupancy -- For Transgress 5CMS Agent0 AD Credits Acquired -- For Transgress 0CMS Agent0 AD Credits Acquired -- For Transgress 1CMS Agent0 AD Credits Acquired -- For Transgress 2CMS Agent0 AD Credits Acquired -- For Transgress 3CMS Agent0 AD Credits Acquired -- For Transgress 4CMS Agent0 AD Credits Acquired -- For Transgress 5[UNC_IIO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d chmask=0x%x fcmsk=0x%x] %s
Number of double word (4 bytes) requests initiated by the main die to the attached device.Number of double word (4 bytes) requests the attached device made of the main die.Asserted if all bits specified by mask matchAsserted if any bits specified by mask matchGen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nSAlso known as Outbound.  Number of requests, to the attached device, initiated by the main die.Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.VTd Access -- context cache missOR Mask/match for debug bus -- Non-PCIE busOR Mask/match for debug bus -- Non-PCIE bus and PCIE busOR Mask/match for debug bus -- Non-PCIE bus and !(PCIE bus)OR Mask/match for debug bus -- PCIE busOR Mask/match for debug bus -- !(Non-PCIE bus) and PCIE busOR Mask/match for debug bus -- !(Non-PCIE bus) and !(PCIE bus)AND Mask/match for debug bus -- Non-PCIE busAND Mask/match for debug bus -- Non-PCIE bus and PCIE busAND Mask/match for debug bus -- Non-PCIE bus and !(PCIE bus)AND Mask/match for debug bus -- PCIE busAND Mask/match for debug bus -- !(Non-PCIE bus) and PCIE busAND Mask/match for debug bus -- Data requested of the CPU -- Atomic requests targeting DRAMData requested of the CPU -- Completion of atomic requests targeting DRAMData requested of the CPU -- Card reading from DRAMData requested by the CPU -- Core reading from any DRAM sourceMEM_READ_PART0:MEM_READ_PART1:MEM_READ_PART2:MEM_READ_PART3:MEM_READ_VTD0:MEM_READ_VTD1Data requested of the CPU -- Card writing to DRAMData requested of the CPU -- MessagesData requested of the CPU -- Card reading from another Card (same or different stack)Data requested of the CPU -- Card writing to another Card (same or different stack)FC_POSTED_REQ:FC_NON_POSTED_REQ:FC_CMPLData requested by the CPU -- Core reading from Cards PCICFG spacceData requested by the CPU -- Core writing to Cards PCICFG spacceData requested by the CPU -- Core reading from Cards IO spacceData requested by the CPU -- Core writing to Cards IO spacceData requested by the CPU -- Core reading from Cards MMIO spacceData requested by the CPU -- Core reading from any sourceData requested by the CPU -- Core writing to Cards MMIO spacceData requested by the CPU -- Core writingMEM_WRITE_PART0:MEM_WRITE_PART1:MEM_WRITE_PART2:MEM_WRITE_PART3:MEM_WRITE_VTD0:MEM_WRITE_VTD1Another card (different IIO stack) reading from this card.PEER_READ_PART0:PEER_READ_PART1:PEER_READ_PART2:PEER_READ_PART3:PEER_READ_VTD0:PEER_READ_VTD1Another card (different IIO stack) writing to this card.PEER_WRITE_PART0:PEER_WRITE_PART1:PEER_WRITE_PART2:PEER_WRITE_PART3:PEER_WRITE_VTD0:PEER_WRITE_VTD1PCIe Completion Buffer Inserts -- Port 0PCIe Completion Buffer Inserts -- Port 1PCIe Completion Buffer Inserts -- Port 2PCIe Completion Buffer Inserts -- Port 3PCIe Completion Buffer Inserts -- Any portDRAM Clock ticks, fixed counter. Counts at half the DDR speed. Speed never changesDRAM Clock ticks, generic countersCounts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencieies.Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMiMC.Number of times not getting the requested major modeAccess to Bank Group 0 (Banks 0-3)Access to Bank Group 1 (Banks 4-7)Access to Bank Group 2 (Banks 8-11)Access to Bank Group 3 (Banks 12-15) -- Read CAS issued with HIGH priority -- Read CAS issued with LOW priority -- Read CAS issued with MEDIUM priority -- Read CAS issued with PANIC NON ISOCH priority (starved)Number of DRAM Refreshes Issued -- DRAM CAS (Column Address Strobe) Commands. -- All CASes issued.DRAM CAS (Column Address Strobe) Commands. -- All DRAM Reads (includes underfills)DRAM CAS (Column Address Strobe) Commands. -- Read CAS issued in Read ISOCH ModeDRAM CAS (Column Address Strobe) Commands. -- All read CAS (w/ and w/out auto-pre)DRAM CAS (Column Address Strobe) Commands. -- Read CAS issued in RMMDRAM CAS (Column Address Strobe) Commands. -- Underfill Read IssuedDRAM CAS (Column Address Strobe) Commands. -- Read CAS issued in WMMDRAM CAS (Column Address Strobe) Commands. -- All DRAM WR_CAS (both Modes)DRAM CAS (Column Address Strobe) Commands. -- Read CAS issued in Write ISOCH ModeDRAM CAS (Column Address Strobe) Commands. -- DRAM WR_CAS (w/ and w/out auto-pre) in Read Major ModeDRAM CAS (Column Address Strobe) Commands. -- DRAM WR_CAS (w/ and w/out auto-pre) in Write Major ModeDRAM Activate Count -- Activate due to BypassUNC_I_TXR2_AD_STALL_CREDIT_CYCLESUNC_I_TXR2_BL_STALL_CREDIT_CYCLESP2P Transactions -- P2P completionsP2P Transactions -- match if local onlyP2P Transactions -- match if local and target matchesP2P Transactions -- P2P MessageP2P Transactions -- Match if remote onlyP2P Transactions -- match if remote and target matchesP2P Transactions -- P2P WritesMisc Events - Set 1 -- Lost Forward -- All Inserts Inbound (p2p + faf + cset) -- All Inserts Outbound (BL, AK, Snoops)Total Write Cache Occupancy -- SnoopsTotal Write Cache Occupancy -- Mem[UNC_M2M=0x%lx event=0x%x umask=0x%x en=%d edge=%d thres=%d] %s
UNC_M2_AG1_BL_CREDITS_ACQUIREDUNC_M2_DIRECT2CORE_NOT_TAKEN_DIRSTATEUNC_M2_DIRECT2CORE_TXN_OVERRIDEUNC_M2_DIRECT2UPI_NOT_TAKEN_CREDITSUNC_M2_DIRECT2UPI_NOT_TAKEN_DIRSTATEUNC_M2_DIRECT2UPI_TXN_OVERRIDEUNC_M2_PREFCAM_DEMAND_PROMOTIONSUNC_M2_RPQ_CYCLES_SPEC_CREDITSUNC_M2_STALL_NO_TXR_HORZ_CRD_AD_AG0UNC_M2_STALL_NO_TXR_HORZ_CRD_AD_AG1UNC_M2_STALL_NO_TXR_HORZ_CRD_BL_AG0UNC_M2_STALL_NO_TXR_HORZ_CRD_BL_AG1UNC_M2_TRACKER_PENDING_OCCUPANCYUNC_M2_TXC_AD_CREDITS_ACQUIREDUNC_M2_TXC_AD_CREDIT_OCCUPANCYUNC_M2_TXC_AD_NO_CREDIT_CYCLESUNC_M2_TXC_AD_NO_CREDIT_STALLEDUNC_M2_TXC_AK_CREDITS_ACQUIREDUNC_M2_TXC_AK_CREDIT_OCCUPANCYUNC_M2_TXC_AK_NO_CREDIT_CYCLESUNC_M2_TXC_AK_NO_CREDIT_STALLEDUNC_M2_TXC_BL_CREDITS_ACQUIREDUNC_M2_TXC_BL_CREDIT_OCCUPANCYUNC_M2_TXC_BL_NO_CREDIT_CYCLESUNC_M2_TXC_BL_NO_CREDIT_STALLEDUNC_M2_WPQ_CYCLES_SPEC_CREDITSUNC_M2_WRITE_TRACKER_CYCLES_FULLUNC_M2_WRITE_TRACKER_CYCLES_NEUNC_M2_WRITE_TRACKER_OCCUPANCYWrite Tracker Occupancy -- Channel 0Write Tracker Occupancy -- Channel 1Write Tracker Occupancy -- Channel 2Write Tracker Inserts -- Channel 0Write Tracker Inserts -- Channel 1Write Tracker Inserts -- Channel 2Write Tracker Cycles Not Empty -- Channel 0Write Tracker Cycles Not Empty -- Channel 1Write Tracker Cycles Not Empty -- Channel 2Write Tracker Cycles Full -- Channel 0Write Tracker Cycles Full -- Channel 1Write Tracker Cycles Full -- Channel 2M2M->iMC WPQ Cycles w/Credits - Special -- Channel 0M2M->iMC WPQ Cycles w/Credits - Special -- Channel 1M2M->iMC WPQ Cycles w/Credits - Special -- Channel 2M2M->iMC WPQ Cycles w/Credits - Regular -- Channel 0M2M->iMC WPQ Cycles w/Credits - Regular -- Channel 1M2M->iMC WPQ Cycles w/Credits - Regular -- Channel 2BL Egress (to CMS) Occupancy -- AllBL Egress (to CMS) Occupancy -- Common Mesh Stop - Near SideBL Egress (to CMS) Occupancy -- Common Mesh Stop - Far SideCycles Stalled with No BL Egress (to CMS) Credits -- Common Mesh Stop - Near SideCycles Stalled with No BL Egress (to CMS) Credits -- Common Mesh Stop - Far SideCycles with No BL Egress (to CMS) Credits -- Common Mesh Stop - Near SideCycles with No BL Egress (to CMS) Credits -- Common Mesh Stop - Far SideBL Egress (to CMS) Allocations -- AllBL Egress (to CMS) Allocations -- Common Mesh Stop - Near SideBL Egress (to CMS) Allocations -- Common Mesh Stop - Far SideBL Egress (to CMS) Not Empty -- AllBL Egress (to CMS) Not Empty -- Common Mesh Stop - Near SideBL Egress (to CMS) Not Empty -- Common Mesh Stop - Far SideBL Egress (to CMS) Full -- AllBL Egress (to CMS) Full -- Common Mesh Stop - Near SideBL Egress (to CMS) Full -- Common Mesh Stop - Far SideBL Egress (to CMS) Credits Occupancy -- Common Mesh Stop - Near SideBL Egress (to CMS) Credits Occupancy -- Common Mesh Stop - Far SideBL Egress (to CMS) Credit Acquired -- Common Mesh Stop - Near SideBL Egress (to CMS) Credit Acquired -- Common Mesh Stop - Far SideAK Egress (to CMS) Sideband -- AK Egress (to CMS) Occupancy -- AllAK Egress (to CMS) Occupancy -- Common Mesh Stop - Near SideAK Egress (to CMS) Occupancy -- Common Mesh Stop - Far SideAK Egress (to CMS) Occupancy -- Read Credit RequestAK Egress (to CMS) Occupancy -- Write Compare RequestAK Egress (to CMS) Occupancy -- Write Credit RequestCycles Stalled with No AK Egress (to CMS) Credits -- Common Mesh Stop - Near SideCycles Stalled with No AK Egress (to CMS) Credits -- Common Mesh Stop - Far SideCycles with No AK Egress (to CMS) Credits -- Common Mesh Stop - Near SideCycles with No AK Egress (to CMS) Credits -- Common Mesh Stop - Far SideAK Egress (to CMS) Allocations -- AllAK Egress (to CMS) Allocations -- Common Mesh Stop - Near SideAK Egress (to CMS) Allocations -- Common Mesh Stop - Far SideAK Egress (to CMS) Allocations -- Prefetch Read Cam HitAK Egress (to CMS) Allocations -- Read Credit RequestAK Egress (to CMS) Allocations -- Write Compare RequestAK Egress (to CMS) Allocations -- Write Credit RequestAK Egress (to CMS) Not Empty -- AllAK Egress (to CMS) Not Empty -- Common Mesh Stop - Near SideAK Egress (to CMS) Not Empty -- Common Mesh Stop - Far SideAK Egress (to CMS) Not Empty -- Read Credit RequestAK Egress (to CMS) Not Empty -- Write Compare RequestAK Egress (to CMS) Not Empty -- Write Credit RequestAK Egress (to CMS) Full -- AllAK Egress (to CMS) Full -- Common Mesh Stop - Near SideAK Egress (to CMS) Full -- Common Mesh Stop - Far SideAK Egress (to CMS) Full -- Read Credit RequestAK Egress (to CMS) Full -- Write Compare RequestAK Egress (to CMS) Full -- Write Credit RequestAK Egress (to CMS) Credits Occupancy -- Common Mesh Stop - Near SideAK Egress (to CMS) Credits Occupancy -- Common Mesh Stop - Far SideAK Egress (to CMS) Credit Acquired -- Common Mesh Stop - Near SideAK Egress (to CMS) Credit Acquired -- Common Mesh Stop - Far SideOutbound Ring Transactions on AK -- CRD Transactions to CboOutbound Ring Transactions on AK -- NDR TransactionsTracker Occupancy -- Channel 0Tracker Occupancy -- Channel 1Tracker Occupancy -- Channel 2Tracker Cycles Not Empty -- Channel 0Tracker Cycles Not Empty -- Channel 1Tracker Cycles Not Empty -- Channel 2Tracker Cycles Full -- Channel 0Tracker Cycles Full -- Channel 1Tracker Cycles Full -- Channel 2M2M to iMC RPQ Cycles w/Credits - Special -- Channel 0M2M to iMC RPQ Cycles w/Credits - Special -- Channel 1M2M to iMC RPQ Cycles w/Credits - Special -- Channel 2M2M to iMC RPQ Cycles w/Credits - Regular -- Channel 0M2M to iMC RPQ Cycles w/Credits - Regular -- Channel 1M2M to iMC RPQ Cycles w/Credits - Regular -- Channel 2Number Packet Header Matches -- MC MatchNumber Packet Header Matches -- Mesh MatchM2M Writes Issued to iMC -- All WritesM2M Writes Issued to iMC -- All, regardless of priority.M2M Writes Issued to iMC -- Full Line Non-ISOCHM2M Writes Issued to iMC -- ISOCH Full LineM2M Writes Issued to iMC -- Partial Non-ISOCHM2M Writes Issued to iMC -- ISOCH PartialM2M Reads Issued to iMC -- All, regardless of priority.M2M Reads Issued to iMC -- Critical PriorityM2M Reads Issued to iMC -- Normal PriorityDirectory Miss -- On NonDirty Line in A StateDirectory Miss -- On NonDirty Line in I StateDirectory Miss -- On NonDirty Line in L StateDirectory Miss -- On NonDirty Line in S StateDirectory Miss -- On Dirty Line in A StateDirectory Miss -- On Dirty Line in I StateDirectory Miss -- On Dirty Line in L StateDirectory Miss -- On Dirty Line in S StateDirectory Lookups -- Any stateDirectory Hit -- On NonDirty Line in A StateDirectory Hit -- On NonDirty Line in I StateDirectory Hit -- On NonDirty Line in L StateDirectory Hit -- On NonDirty Line in S StateDirectory Hit -- On Dirty Line in A StateDirectory Hit -- On Dirty Line in I StateDirectory Hit -- On Dirty Line in L StateDirectory Hit -- On Dirty Line in S StateM2M to iMC Bypass -- Not TakenCMS Agent0 Credits Occupancy -- For Transgress 0CMS Agent0 Credits Occupancy -- For Transgress 1CMS Agent0 Credits Occupancy -- For Transgress 2CMS Agent0 Credits Occupancy -- For Transgress 3CMS Agent0 Credits Occupancy -- For Transgress 4CMS Agent0 Credits Occupancy -- For Transgress 5CMS Agent0 Credits Acquired -- For Transgress 0CMS Agent0 Credits Acquired -- For Transgress 1CMS Agent0 Credits Acquired -- For Transgress 2CMS Agent0 Credits Acquired -- For Transgress 3CMS Agent0 Credits Acquired -- For Transgress 4CMS Agent0 Credits Acquired -- For Transgress 5[UNC_M3UPI=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
UNC_M3_AG1_BL_CREDITS_ACQUIREDCounts the number of uclks in the M3 uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.Count cases BL sends direct to coreCases where SMI3 sends D2U commandNo vn0 and vna credits available to send to M2Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)VN0 message requested but lost arbitrationVN1 message requested but lost arbitrationVN0 message was not able to request arbitration while some other message won arbitrationVN1 message was not able to request arbitration while some other message won arbitrationVN0 message is blocked from requesting arbitration due to lack of remote UPI creditsVN1 message is blocked from requesting arbitration due to lack of remote UPI creditsNumber ot times message is bypassed around the Ingress QueueCount cases where Ingress VN0 packets lost the contest for Flit Slot 0.Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.UNC_M3_RXC_FLITS_DATA_NOT_SENTData flit is ready for transmission but could not be sentEvents related to Header Flit Generation - Set 1Events related to Header Flit Generation - Set 2header flit is ready for transmission but could not be sentCounts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.UNC_M3_STALL_NO_TXR_HORZ_CRD_AD_AG0UNC_M3_STALL_NO_TXR_HORZ_CRD_AD_AG1UNC_M3_STALL_NO_TXR_HORZ_CRD_BL_AG0UNC_M3_STALL_NO_TXR_HORZ_CRD_BL_AG1AD arb but no win; arb request asserted but not wonCounts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)Number of cycles the AD Egress queue is Not EmptyCounts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latencyOutcome of SnpF pending arbitrationUNC_M3_TXC_AD_SPEC_ARB_CRD_AVAILAD speculative arb request with prior cycle credit check complete and credit availUNC_M3_TXC_AD_SPEC_ARB_NEW_MSGAD speculative arb request due to new message arriving on a specific channel (MC/VN)UNC_M3_TXC_AD_SPEC_ARB_NO_OTHER_PENDAD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)BL arb but no win; arb request asserted but not wonNumber of cycles the BL Egress queue is Not EmptyUNC_M3_TXC_BL_SPEC_ARB_NEW_MSGBL speculative arb request due to new message arriving on a specific channel (MC/VN)UNC_M3_TXC_BL_SPEC_ARB_NO_OTHER_PENDBL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)UNC_M3_UPI_PEER_AD_CREDITS_EMPTYNo credits available to send to UPIs on the AD RingUNC_M3_UPI_PEER_BL_CREDITS_EMPTYNo credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 targetNumber of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.Number of Cycles there were no VN0 CreditsNumber of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.Number of Cycles there were no VN1 CreditsUPI0 BL Credits Empty -- VN0 RSP MessagesUPI0 BL Credits Empty -- VN0 REQ MessagesUPI0 BL Credits Empty -- VN0 SNP MessagesUPI0 BL Credits Empty -- VN1 RSP MessagesUPI0 BL Credits Empty -- VN1 REQ MessagesUPI0 BL Credits Empty -- VN1 SNP MessagesUPI0 AD Credits Empty -- VN0 REQ MessagesUPI0 AD Credits Empty -- VN0 RSP MessagesUPI0 AD Credits Empty -- VN0 SNP MessagesUPI0 AD Credits Empty -- VN1 REQ MessagesUPI0 AD Credits Empty -- VN1 RSP MessagesUPI0 AD Credits Empty -- VN1 SNP MessagesSpeculative ARB for AD Failed - No Credit -- VN0 NCB MessagesSpeculative ARB for AD Failed - No Credit -- VN0 NCS MessagesSpeculative ARB for AD Failed - No Credit -- VN0 RSP MessagesSpeculative ARB for AD Failed - No Credit -- VN0 WB MessagesSpeculative ARB for AD Failed - No Credit -- VN1 NCS MessagesSpeculative ARB for AD Failed - No Credit -- VN1 NCB MessagesSpeculative ARB for AD Failed - No Credit -- VN1 RSP MessagesSpeculative ARB for AD Failed - No Credit -- VN1 WB MessagesSpeculative ARB for BL  - New Message -- VN0 WB MessagesSpeculative ARB for BL  - New Message -- VN0 NCS MessagesSpeculative ARB for BL  - New Message -- VN1 WB MessagesSpeculative ARB for BL  - New Message -- VN1 NCB MessagesSpeculative ARB for BL  - New Message -- VN1 RSP MessagesBL Flow Q Occupancy -- VN0 NCB MessagesBL Flow Q Occupancy -- VN0 NCS MessagesBL Flow Q Occupancy -- VN0 RSP MessagesBL Flow Q Occupancy -- VN0 WB MessagesBL Flow Q Occupancy -- VN1_NCS MessagesBL Flow Q Occupancy -- VN1_NCB MessagesBL Flow Q Occupancy -- VN1 RSP MessagesBL Flow Q Occupancy -- VN1 WB MessagesBL Flow Q Inserts -- VN0 RSP MessagesBL Flow Q Inserts -- VN0 WB MessagesBL Flow Q Inserts -- VN0 NCS MessagesBL Flow Q Inserts -- VN0 NCB MessagesBL Flow Q Inserts -- VN1 RSP MessagesBL Flow Q Inserts -- VN1 WB MessagesBL Flow Q Inserts -- VN1_NCB MessagesBL Flow Q Inserts -- VN1_NCS MessagesBL Flow Q Not Empty -- VN0 REQ MessagesBL Flow Q Not Empty -- VN0 RSP MessagesBL Flow Q Not Empty -- VN0 SNP MessagesBL Flow Q Not Empty -- VN0 WB MessagesBL Flow Q Not Empty -- VN1 REQ MessagesBL Flow Q Not Empty -- VN1 RSP MessagesBL Flow Q Not Empty -- VN1 SNP MessagesBL Flow Q Not Empty -- VN1 WB MessagesFailed ARB for BL -- VN0 NCB MessagesFailed ARB for BL -- VN0 NCS MessagesFailed ARB for BL -- VN0 RSP MessagesFailed ARB for BL -- VN0 WB MessagesFailed ARB for BL -- VN1 NCS MessagesFailed ARB for BL -- VN1 NCB MessagesFailed ARB for BL -- VN1 RSP MessagesFailed ARB for BL -- VN1 WB MessagesSpeculative ARB for AD  - No Credit -- VN0 REQ MessagesSpeculative ARB for AD  - No Credit -- VN0 RSP MessagesSpeculative ARB for AD  - No Credit -- VN0 SNP MessagesSpeculative ARB for AD  - No Credit -- VN0 WB MessagesSpeculative ARB for AD  - No Credit -- VN1 REQ MessagesSpeculative ARB for AD  - No Credit -- VN1 RSP MessagesSpeculative ARB for AD  - No Credit -- VN1 SNP MessagesSpeculative ARB for AD  - No Credit -- VN1 WB MessagesSpeculative ARB for AD  - New Message -- VN0 REQ MessagesSpeculative ARB for AD  - New Message -- VN0 SNP MessagesSpeculative ARB for AD  - New Message -- VN0 WB MessagesSpeculative ARB for AD  - New Message -- VN1 REQ MessagesSpeculative ARB for AD  - New Message -- VN1 SNP MessagesSpeculative ARB for AD  - New Message -- VN1 WB MessagesSpeculative ARB for AD  -  Credit Available -- VN0 REQ MessagesSpeculative ARB for AD  -  Credit Available -- VN0 SNP MessagesSpeculative ARB for AD  -  Credit Available -- VN0 WB MessagesSpeculative ARB for AD  -  Credit Available -- VN1 REQ MessagesSpeculative ARB for AD  -  Credit Available -- VN1 SNP MessagesSpeculative ARB for AD  -  Credit Available -- VN1 WB MessagesSnoop Arbitration -- FlowQ WonSnoop Arbitration -- FlowQ SnpF WonNumber of Snoop Targets -- CHA on VN0Number of Snoop Targets -- Non Idle cycles on VN0Number of Snoop Targets -- Peer UPI0 on VN0Number of Snoop Targets -- Peer UPI1 on VN0Number of Snoop Targets -- CHA on VN1Number of Snoop Targets -- Non Idle cycles on VN1Number of Snoop Targets -- Peer UPI0 on VN1Number of Snoop Targets -- Peer UPI1 on VN1AD Flow Q Occupancy -- VN0 REQ MessagesAD Flow Q Occupancy -- VN0 RSP MessagesAD Flow Q Occupancy -- VN0 SNP MessagesAD Flow Q Occupancy -- VN0 WB MessagesAD Flow Q Occupancy -- VN1 REQ MessagesAD Flow Q Occupancy -- VN1 RSP MessagesAD Flow Q Occupancy -- VN1 SNP MessagesAD Flow Q Inserts -- VN0 REQ MessagesAD Flow Q Inserts -- VN0 RSP MessagesAD Flow Q Inserts -- VN0 SNP MessagesAD Flow Q Inserts -- VN0 WB MessagesAD Flow Q Inserts -- VN1 REQ MessagesAD Flow Q Inserts -- VN1 RSP MessagesAD Flow Q Inserts -- VN1 SNP MessagesAD Flow Q Not Empty -- VN0 REQ MessagesAD Flow Q Not Empty -- VN0 RSP MessagesAD Flow Q Not Empty -- VN0 SNP MessagesAD Flow Q Not Empty -- VN0 WB MessagesAD Flow Q Not Empty -- VN1 REQ MessagesAD Flow Q Not Empty -- VN1 RSP MessagesAD Flow Q Not Empty -- VN1 SNP MessagesAD Flow Q Not Empty -- VN1 WB MessagesFailed ARB for AD -- VN0 REQ MessagesFailed ARB for AD -- VN0 RSP MessagesFailed ARB for AD -- VN0 SNP MessagesFailed ARB for AD -- VN0 WB MessagesFailed ARB for AD -- VN1 REQ MessagesFailed ARB for AD -- VN1 RSP MessagesFailed ARB for AD -- VN1 SNP MessagesFailed ARB for AD -- VN1 WB MessagesRemote VNA Credits -- Any In UseRemote VNA Credits -- CorrectedRemote VNA Credits -- Level < 1Remote VNA Credits -- Level < 4Remote VNA Credits -- Level < 5SMI3 Prefetch Messages -- Lost ArbitrationSMI3 Prefetch Messages -- ArrivedSMI3 Prefetch Messages -- Dropped - OldSMI3 Prefetch Messages -- Dropped - WrapSMI3 Prefetch Messages -- SlottedVN1 message cant slot into flit -- REQ on AADVN1 message cant slot into flit -- RSP on AADVN1 message cant slot into flit -- SNP on AADVN1 message cant slot into flit -- NCB on BBLVN1 message cant slot into flit -- NCS on BBLVN1 message cant slot into flit -- RSP on BBLVN1 message cant slot into flit -- WB on BBLVN0 message cant slot into flit -- REQ on AADVN0 message cant slot into flit -- RSP on AADVN0 message cant slot into flit -- SNP on AADVN0 message cant slot into flit -- NCB on BBLVN0 message cant slot into flit -- NCS on BBLVN0 message cant slot into flit -- RSP on BBLVN0 message cant slot into flit -- WB on BBLVN1 Ingress (from CMS) Queue - Occupancy -- REQ on ADVN1 Ingress (from CMS) Queue - Occupancy -- RSP on ADVN1 Ingress (from CMS) Queue - Occupancy -- SNP on ADVN1 Ingress (from CMS) Queue - Occupancy -- NCB on BLVN1 Ingress (from CMS) Queue - Occupancy -- NCS on BLVN1 Ingress (from CMS) Queue - Occupancy -- RSP on BLVN1 Ingress (from CMS) Queue - Occupancy -- WB on BLVN0 Ingress (from CMS) Queue - Occupancy -- REQ on ADVN0 Ingress (from CMS) Queue - Occupancy -- RSP on ADVN0 Ingress (from CMS) Queue - Occupancy -- SNP on ADVN0 Ingress (from CMS) Queue - Occupancy -- NCB on BLVN0 Ingress (from CMS) Queue - Occupancy -- NCS on BLVN0 Ingress (from CMS) Queue - Occupancy -- RSP on BLVN0 Ingress (from CMS) Queue - Occupancy -- WB on BLVN1 Ingress (from CMS) Queue - Inserts -- REQ on ADVN1 Ingress (from CMS) Queue - Inserts -- RSP on ADVN1 Ingress (from CMS) Queue - Inserts -- SNP on ADVN1 Ingress (from CMS) Queue - Inserts -- NCB on BLVN1 Ingress (from CMS) Queue - Inserts -- NCS on BLVN1 Ingress (from CMS) Queue - Inserts -- RSP on BLVN1 Ingress (from CMS) Queue - Inserts -- WB on BLVN0 Ingress (from CMS) Queue - Inserts -- REQ on ADVN0 Ingress (from CMS) Queue - Inserts -- RSP on ADVN0 Ingress (from CMS) Queue - Inserts -- SNP on ADVN0 Ingress (from CMS) Queue - Inserts -- NCB on BLVN0 Ingress (from CMS) Queue - Inserts -- NCS on BLVN0 Ingress (from CMS) Queue - Inserts -- RSP on BLVN0 Ingress (from CMS) Queue - Inserts -- WB on BLMessage Held -- Parallel AD LostMessage Held -- Parallel AttemptMessage Held -- Parallel BL LostMessage Held -- Parallel SuccessHeader Not Sent -- No BGF CreditsHeader Not Sent -- No BGF Credits + No Extra Message SlottedHeader Not Sent -- No TxQ CreditsHeader Not Sent -- No TxQ Credits + No Extra Message SlottedHeader Not Sent -- Sent - One Slot TakenHeader Not Sent -- Sent - Three Slots TakenHeader Not Sent -- Sent - Two Slots TakenFlit Gen - Header 2 -- Rate-matching StallFlit Gen - Header 2 -- Rate-matching Stall - No MessageFlit Gen - Header 1 -- AccumulateFlit Gen - Header 1 -- Accumulate ReadyFlit Gen - Header 1 -- Accumulate WastedFlit Gen - Header 1 -- Run-Ahead - BlockedFlit Gen - Header 1 -- Run-Ahead - MessageFlit Gen - Header 1 -- Parallel OkFlit Gen - Header 1 -- Parallel Flit FinishedFlit Gen - Header 1 -- Parallel MessageSlotting BL Message Into Header Flit -- AllSlotting BL Message Into Header Flit -- Needs Data FlitSlotting BL Message Into Header Flit -- Wait on Pump 0Slotting BL Message Into Header Flit -- Don't Need Pump 1Slotting BL Message Into Header Flit -- Don't Need Pump 1 - BubbleSlotting BL Message Into Header Flit -- Don't Need Pump 1 - Not AvailSlotting BL Message Into Header Flit -- Wait on Pump 1Sent Header Flit -- One MessageSent Header Flit -- One Message in non-VNASent Header Flit -- Two MessagesSent Header Flit -- Three MessagesGenerating BL Data Flit Sequence -- Wait on Pump 0Generating BL Data Flit Sequence -- Generating BL Data Flit Sequence -- Wait on Pump 1Data Flit Not Sent -- No BGF CreditsData Flit Not Sent -- No TxQ CreditsVN1 Ingress (from CMS) Queue - Cycles Not Empty -- REQ on ADVN1 Ingress (from CMS) Queue - Cycles Not Empty -- RSP on ADVN1 Ingress (from CMS) Queue - Cycles Not Empty -- SNP on ADVN1 Ingress (from CMS) Queue - Cycles Not Empty -- NCB on BLVN1 Ingress (from CMS) Queue - Cycles Not Empty -- NCS on BLVN1 Ingress (from CMS) Queue - Cycles Not Empty -- RSP on BLVN1 Ingress (from CMS) Queue - Cycles Not Empty -- WB on BLVN0 Ingress (from CMS) Queue - Cycles Not Empty -- REQ on ADVN0 Ingress (from CMS) Queue - Cycles Not Empty -- RSP on ADVN0 Ingress (from CMS) Queue - Cycles Not Empty -- SNP on ADVN0 Ingress (from CMS) Queue - Cycles Not Empty -- NCB on BLVN0 Ingress (from CMS) Queue - Cycles Not Empty -- NCS on BLVN0 Ingress (from CMS) Queue - Cycles Not Empty -- RSP on BLVN0 Ingress (from CMS) Queue - Cycles Not Empty -- WB on BLCredit Occupancy -- D2K CreditsCredit Occupancy -- Packets in BGF FIFOCredit Occupancy -- Packets in BGF PathCredit Occupancy -- Transmit CreditsCredit Occupancy -- VNA In UseMiscellaneous Credit Events -- Any In BGF FIFOMiscellaneous Credit Events -- Any in BGF PathMiscellaneous Credit Events -- No D2K For ArbVN1 message lost contest for flit -- REQ on ADVN1 message lost contest for flit -- RSP on ADVN1 message lost contest for flit -- SNP on ADVN1 message lost contest for flit -- NCB on BLVN1 message lost contest for flit -- NCS on BLVN1 message lost contest for flit -- RSP on BLVN1 message lost contest for flit -- WB on BLVN0 message lost contest for flit -- REQ on ADVN0 message lost contest for flit -- RSP on ADVN0 message lost contest for flit -- SNP on ADVN0 message lost contest for flit -- NCB on BLVN0 message lost contest for flit -- NCS on BLVN0 message lost contest for flit -- RSP on BLVN0 message lost contest for flit -- WB on BLIngress Queue Bypasses -- AD to Slot 0 on BL ArbIngress Queue Bypasses -- AD to Slot 0 on IdleIngress Queue Bypasses -- AD + BL to Slot 1Ingress Queue Bypasses -- AD + BL to Slot 2No Credits to Arb for VN1 -- REQ on ADNo Credits to Arb for VN1 -- RSP on ADNo Credits to Arb for VN1 -- SNP on ADNo Credits to Arb for VN1 -- NCB on BLNo Credits to Arb for VN1 -- NCS on BLNo Credits to Arb for VN1 -- RSP on BLNo Credits to Arb for VN1 -- WB on BLNo Credits to Arb for VN0 -- REQ on ADNo Credits to Arb for VN0 -- RSP on ADNo Credits to Arb for VN0 -- SNP on ADNo Credits to Arb for VN0 -- NCB on BLNo Credits to Arb for VN0 -- NCS on BLNo Credits to Arb for VN0 -- RSP on BLNo Credits to Arb for VN0 -- WB on BLCant Arb for VN1 -- REQ on AADCant Arb for VN1 -- RSP on AADCant Arb for VN1 -- SNP on AADCant Arb for VN1 -- NCB on BBLCant Arb for VN1 -- NCS on BBLCant Arb for VN1 -- RSP on BBLCant Arb for VN0 -- REQ on AADCant Arb for VN0 -- RSP on AADCant Arb for VN0 -- SNP on AADCant Arb for VN0 -- NCB on BBLCant Arb for VN0 -- NCS on BBLCant Arb for VN0 -- RSP on BBLArb Miscellaneous -- AD, BL Parallel WinArb Miscellaneous -- No Progress on Pending AD VN0Arb Miscellaneous -- No Progress on Pending AD VN1Arb Miscellaneous -- No Progress on Pending BL VN0Arb Miscellaneous -- No Progress on Pending BL VN1Arb Miscellaneous -- Parallel Bias to VN0Arb Miscellaneous -- Parallel Bias to VN1Multi Slot Flit Received -- AD - Slot 0Multi Slot Flit Received -- AD - Slot 1Multi Slot Flit Received -- AD - Slot 2Multi Slot Flit Received -- AK - Slot 0Multi Slot Flit Received -- AK - Slot 2Multi Slot Flit Received -- BL - Slot 0M2 BL Credits Empty -- IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)M2 BL Credits Empty -- All IIO targets for NCS are in single mask. ORs them togetherM2 BL Credits Empty -- Selected M2p BL NCS creditsCBox AD Credits Empty -- RequestsCBox AD Credits Empty -- SnoopsCBox AD Credits Empty -- VNA MessagesCBox AD Credits Empty -- WritebacksCounts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.Virtual Logical Wire (legacy) message were received from Uncore.Number of times an IDI Lock/SplitLock sequence was startedCycles PHOLD Assert to Ack -- Assert to ACK[UNC_UPI=0x%lx event=0x%x sel_ext=%d umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
Counts the number of clocks in the UPI LL.  This clock runs at 1/8th the GT/s speed of the UPI link.  For example, a 8GT/s link will have qfclk or 1GHz.  Current products do not support dynamic link speeds, so this frequency is fixexed.Counts the number of Data Response(DRS) packets UPI attempted to send directly to the core or to a different UPI link.  Note:  This only counts attempts on valid candidates such as DRS packets destined for CHAs.Number of UPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a UPI link.  Use edge detect to count the number of instances when the UPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.Counts the number of times a link sends/receives a LinkReqNAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqNAck refers to receiving an NAck (meaning this agents Tx originally requested the power change).  A Tx LinkReqNAck refers to sending this command (meaning the peer agents Tx originally requested the power change and this agent accepted itit).Counts the number of times a link sends/receives a LinkReqAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqAck refers to receiving an Ack (meaning this agents Tx originally requested the power change).  A Tx LinkReqAck refers to sending this command (meaning the peer agents Tx originally requested the power change and this agent accepted itit).Number of UPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses.  Use edge detect to count the number of instances when the UPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.UNC_UPI_RXL_CREDITS_CONSUMED_VN0UNC_UPI_RXL_CREDITS_CONSUMED_VN1UNC_UPI_RXL_CREDITS_CONSUMED_VNAShows legal flit time (hides impact of L0p and L0c).Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.UNC_UPI_TXL0P_POWER_CYCLES_LL_ENTERUNC_UPI_TXL0P_POWER_CYCLES_M3_EXITCounts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.Number of allocations into the UPI Tx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCYValid Flits Sent -- All Null SlotsValid Flits Sent -- LLCRD Not EmptyValid Flits Sent -- All Non DataValid Flits Sent -- Slot NULL or LLCRD EmptyValid Flits Sent -- Protocol HeaderRxQ Occupancy - All Packets -- Slot 0RxQ Occupancy - All Packets -- Slot 1RxQ Occupancy - All Packets -- Slot 2RxQ Flit Buffer Allocations -- Slot 0RxQ Flit Buffer Allocations -- Slot 1RxQ Flit Buffer Allocations -- Slot 2Valid Flits Received -- All DataValid Flits Received -- All Null SlotsValid Flits Received -- LLCRD Not EmptyValid Flits Received -- LLCTRLValid Flits Received -- All Non DataValid Flits Received -- Slot NULL or LLCRD EmptyValid Flits Received -- Protocol HeaderValid Flits Received -- Slot 0Valid Flits Received -- Slot 1Valid Flits Received -- Slot 2RxQ Flit Buffer Bypassed -- Slot 0RxQ Flit Buffer Bypassed -- Slot 1RxQ Flit Buffer Bypassed -- Slot 2Matches on Receive path of a UPI Port -- Non-Coherent BypassMatches on Receive path of a UPI Port -- Non-Coherent Bypass - NCWRMatches on Receive path of a UPI Port -- Non-Coherent Bypass - WCWRMatches on Receive path of a UPI Port -- Non-Coherent Bypass - INTPHYSICALMatches on Receive path of a UPI Port -- Non-Coherent Bypass - INTPRIOUPDMatches on Receive path of a UPI Port -- Non-Coherent Bypass - NCWRPTLMatches on Receive path of a UPI Port -- Non-Coherent Bypass - NCP2PBMatches on Receive path of a UPI Port -- Non-Coherent StandardMatches on Receive path of a UPI Port -- Non-Coherent Standard - NCRDMatches on Receive path of a UPI Port -- Non-Coherent Standard - INTACKMatches on Receive path of a UPI Port -- Non-Coherent Standard - NCRDPTLMatches on Receive path of a UPI Port -- Non-Coherent Standard - NCLTRDMatches on Receive path of a UPI Port -- Non-Coherent Standard - IORDMatches on Receive path of a UPI Port -- Non-Coherent Standard - CFGWRMatches on Receive path of a UPI Port -- Non-Coherent Standard - LTWRMatches on Receive path of a UPI Port -- Non-Coherent Standard - NCIOWRMatches on Receive path of a UPI Port -- Non-Coherent Standard - NCP2PSMatches on Receive path of a UPI Port -- RequestMatches on Receive path of a UPI Port -- Request Opcode - ITOEMatches on Receive path of a UPI Port -- Request Opcode - ReadInvMatches on Receive path of a UPI Port -- Response - ConflictMatches on Receive path of a UPI Port -- Response - InvalidMatches on Receive path of a UPI Port -- Response - DataMatches on Receive path of a UPI Port -- Response - Data - DATA_MMatches on Receive path of a UPI Port -- Response - Data - DATA_EMatches on Receive path of a UPI Port -- Response - Data - DATA_SIMatches on Receive path of a UPI Port -- Response - Data - DATA_E_CMPOMatches on Receive path of a UPI Port -- Response - Data - DATA_SI_CMPOMatches on Receive path of a UPI Port -- Response - Data - RSPFWDIWBMatches on Receive path of a UPI Port -- Response - Data - RSPIWBMatches on Receive path of a UPI Port -- Response - Data - RSPSWBMatches on Receive path of a UPI Port -- Response - Data - DEBUGDATAMatches on Receive path of a UPI Port -- Response - No DataMatches on Receive path of a UPI Port -- Response - No Data - FWDSMatches on Receive path of a UPI Port -- Response - No Data - MIRCMPUMatches on Receive path of a UPI Port -- Response - No Data - CNFLTMatches on Receive path of a UPI Port -- Response - No Data - FWDCNFLTOMatches on Receive path of a UPI Port -- Response - No Data - CMPOMatches on Receive path of a UPI Port -- SnoopMatches on Receive path of a UPI Port -- Snoop Opcode - FCURMatches on Receive path of a UPI Port -- Snoop Opcode - FCODEMatches on Receive path of a UPI Port -- Snoop Opcode - FDATAMatches on Receive path of a UPI Port -- Snoop Opcode - FDATAMIGMatches on Receive path of a UPI Port -- Snoop Opcode - FINVMatches on Receive path of a UPI Port -- WritebackMatches on Receive path of a UPI Port -- Writeback - MTOIMatches on Receive path of a UPI Port -- Writeback - MTOSMatches on Receive path of a UPI Port -- Writeback - MTOEMatches on Receive path of a UPI Port -- Writeback - NONSNPWRMatches on Receive path of a UPI Port -- Writeback - MTOIPTLMatches on Receive path of a UPI Port -- Writeback - MTOEPTLMatches on Receive path of a UPI Port -- Writeback - NONSNPWRTLMatches on Receive path of a UPI Port -- Writeback - PUSHMTOIMatches on Receive path of a UPI Port -- Writeback - FLUSHMatches on Receive path of a UPI Port -- Writeback - EVCTCLNFilter packets targeting this socketFilter packets targeting another socketFilter on Data packets (mutually exclusive with FILT_NON_DATA)Filter on non-Data packets (mutually exclusive with FILT_DATA)Filter on dual-slot packets (mutually exclusive with FILT_SINGLE_SLOT)Filter on single-slot packets (mutually exclusive with FILT_DUAL_SLOT)Filter on isochronous  packetsFilter on LLCRD nonzero (only applies to slot2 with opcode match)Filter on implied NULL (only applies to slot2 with opcode match)Direct packet attempts -- Direct 2 CoreDirect packet attempts -- Direct 2 UPI[UNC_CHA=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d tid_en=%d umask_ext=0x%x] %s
This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCALUNC_CHA_PMM_MEMMODE_NM_INVITOXThis event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TORUNC_CHA_PMM_MEMMODE_NM_SETCONFLICTSThis event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRUNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2CMS Agent0 AD Credits AcquiredCMS Agent0 AD Credits OccupancyCMS Agent0 BL Credits AcquiredCMS Agent0 BL Credits OccupancyCMS Agent1 AD Credits AcquiredCMS Agent1 AD Credits OccupancyCMS Agent1 BL Credits AcquiredCMS Agent1 BL Credits OccupancyClockticks of the uncore caching and home agent (CHA)Counter 0 Occupancy (experimental)Multi-socket cacheline directory state lookupsMulti-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipeEgress Blocking due to Ordering requirementsRead request from a remote socket which hit in the HitMe Cache to a line In the E stateCounts Number of times HitMe Cache is accessedCounts Number of Misses in HitMe CacheCounts the number of Allocate/Update to HitMe CacheNormal priority reads issued to the memory controller from the CHACHA to iMC Full Line Writes IssuedCache and Snoop Filter Lookups; Data Read RequestNumber of times that an RFO hit in S state.Miscellaneous Events (mostly from MS2IDI)UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCALPMM Memory Mode related eventsUNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODCUNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFOCHA iMC CHNx READ Credits EmptyLocal INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agentMessages that bounced on the Horizontal Ring.Messages that bounced on the Vertical Ring.UNC_CHA_RING_SINK_STARVED_HORZSink Starvation on Horizontal RingUNC_CHA_RING_SINK_STARVED_VERTSink Starvation on Vertical RingSource Throttle (experimental)Ingress (from CMS) AllocationsIPQ Requests (from CMS) Rejected - Set 0IPQ Requests (from CMS) Rejected - Set 1IRQ Requests (from CMS) Rejected - Set 0Ingress (from CMS) Request Queue Rejects; PhyAddr MatchPRQ Requests (from CMS) Rejected - Set 0PRQ Requests (from CMS) Rejected - Set 1Transgress Injection StarvationTransgress Injection Starvation (experimental)Transgress Ingress AllocationsSnoop filter capacity evictions for E-state entries.Snoop Responses Received LocalUNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0Stall on No AD Agent0 Transgress CreditsUNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1Stall on No AD Agent1 Transgress CreditsUNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0Stall on No BL Agent0 Transgress CreditsUNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1Stall on No BL Agent1 Transgress CreditsUNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1Cycles CMS Horizontal Egress Queue is FullCycles CMS Horizontal Egress Queue is Not EmptyCMS Horizontal Egress OccupancyCMS Horizontal Egress Injection StarvationCycles CMS Vertical Egress Queue Is FullCycles CMS Vertical Egress Queue Is Not EmptyCMS Vertical Egress Injection StarvationCHA iMC CHNx WRITE Credits EmptyDropped (on 0?) - Conflict (experimental)Dropped (on 0?) - No Credits (experimental)Dropped (on 1?) - Conflict (experimental)Dropped (on 1?) - No Credits (experimental)Pushed to Memory (experimental)AD - Uncredited (experimental)AKC - Uncredited (experimental)BL - Uncredited (experimental)SF/LLC Evictions (experimental)CLFlushes issued by iA Cores (experimental)CLFlushOpts issued by iA Cores (experimental)DRdPte issued by iA Cores due to a page walk (experimental)DRd_Opts issued by iA Cores (experimental)DRd_Opt_Prefs issued by iA Cores (experimental)DRd_Prefs issued by iA Cores (experimental)All requests from iA Cores that Hit the LLCCRds issued by iA Cores that Hit the LLC (experimental)CRd_Prefs issued by iA Cores that hit the LLC (experimental)DRds issued by iA Cores that Hit the LLC (experimental)DRdPte issued by iA Cores due to a page walk that hit the LLC (experimental)DRd_Opts issued by iA Cores that hit the LLC (experimental)DRd_Opt_Prefs issued by iA Cores that hit the LLC (experimental)DRd_Prefs issued by iA Cores that Hit the LLC (experimental)ItoMs issued by iA Cores that Hit LLC (experimental)LLCPrefCode issued by iA Cores that hit the LLC (experimental)LLCPrefData issued by iA Cores that hit the LLC (experimental)LLCPrefRFO issued by iA Cores that hit the LLC (experimental)RFOs issued by iA Cores that Hit the LLC (experimental)RFO_Prefs issued by iA Cores that Hit the LLC (experimental)ItoMs issued by iA Cores (experimental)ItoMCacheNears issued by iA Cores (experimental)LLCPrefCode issued by iA Cores (experimental)LLCPrefData issued by iA Cores (experimental)LLCPrefRFO issued by iA Cores (experimental)All requests from iA Cores that Missed the LLCCRds issued by iA Cores that Missed the LLCCRd issued by iA Cores that Missed the LLC - HOMed locally (experimental)CRd_Prefs issued by iA Cores that Missed the LLC (experimental)CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally (experimental)CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely (experimental)CRd issued by iA Cores that Missed the LLC - HOMed remotely (experimental)DRds issued by iA Cores that Missed the LLCDRdPte issued by iA Cores due to a page walk that missed the LLC (experimental)DRds issued by iA Cores targeting DDR Mem that Missed the LLCDRds issued by iA Cores that Missed the LLC - HOMed locallyDRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally (experimental)DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally (experimental)DRd_Opt issued by iA Cores that missed the LLC (experimental)DRd_Opt_Prefs issued by iA Cores that missed the LLC (experimental)DRds issued by iA Cores targeting PMM Mem that Missed the LLCDRd_Prefs issued by iA Cores that Missed the LLC (experimental)DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC (experimental)DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally (experimental)DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally (experimental)DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC (experimental)DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely (experimental)DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely (experimental)DRds issued by iA Cores that Missed the LLC - HOMed remotelyDRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely (experimental)DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely (experimental)IA_MISS_FULL_STREAMING_WR_LOCAL_DDRIA_MISS_FULL_STREAMING_WR_LOCAL_PMMIA_MISS_FULL_STREAMING_WR_REMOTE_DDRIA_MISS_FULL_STREAMING_WR_REMOTE_PMMItoMs issued by iA Cores that Missed LLC (experimental)LLCPrefCode issued by iA Cores that missed the LLC (experimental)LLCPrefData issued by iA Cores that missed the LLC (experimental)LLCPrefRFO issued by iA Cores that missed the LLC (experimental)WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally (experimental)WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally (experimental)WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally (experimental)WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally (experimental)IA_MISS_PARTIAL_STREAMING_WR_DDRIA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDRIA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMMIA_MISS_PARTIAL_STREAMING_WR_PMMIA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDRIA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMMWCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely (experimental)WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely (experimental)WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely (experimental)WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely (experimental)RFOs issued by iA Cores that Missed the LLCRFOs issued by iA Cores that Missed the LLC - HOMed locally (experimental)RFO_Prefs issued by iA Cores that Missed the LLC (experimental)RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally (experimental)RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely (experimental)RFOs issued by iA Cores that Missed the LLC - HOMed remotely (experimental)SpecItoMs issued by iA Cores that missed the LLC (experimental)UCRdFs issued by iA Cores that Missed LLC (experimental)WCiLs issued by iA Cores that Missed the LLC (experimental)WCiLF issued by iA Cores that Missed the LLC (experimental)WCiLFs issued by iA Cores targeting DDR that missed the LLC (experimental)WCiLFs issued by iA Cores targeting PMM that missed the LLC (experimental)WCiLs issued by iA Cores targeting DDR that missed the LLC (experimental)WCiLs issued by iA Cores targeting PMM that missed the LLC (experimental)WiLs issued by iA Cores that Missed LLC (experimental)RFO_Prefs issued by iA Cores (experimental)SpecItoMs issued by iA Cores (experimental)WbMtoIs issued by iA Cores (experimental)WCiLs issued by iA Cores (experimental)WCiLF issued by iA Cores (experimental)CLFlushes issued by IO Devices (experimental)All requests from IO Devices that hit the LLCItoMs issued by IO Devices that Hit the LLC (experimental)ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC (experimental)PCIRdCurs issued by IO Devices that hit the LLC (experimental)RFOs issued by IO Devices that hit the LLC (experimental)ItoMs issued by IO Devices (experimental)ItoMCacheNears, indicating a partial write request, from IO Devices (experimental)All requests from IO Devices that missed the LLCItoMs issued by IO Devices that missed the LLC (experimental)ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC (experimental)PCIRdCurs issued by IO Devices that missed the LLCRFOs issued by IO Devices that missed the LLC (experimental)PCIRdCurs issued by IO DevicesRFOs issued by IO Devices (experimental)WbMtoIs issued by IO Devices (experimental)Just Local Targets (experimental)All from Local iA and IO (experimental)All from Local iA (experimental)All from Local IO (experimental)Match the Opcode in b[29:19] of the extended umask field (experimental)Just NonCoherent (experimental)Just NotNearMem (experimental)Match the PreMorphed Opcode in b[29:19] of the extended umask field (experimental)Just Remote Targets (experimental)DRds issued by iA Cores (experimental)DRd PTEs issued by iA Cores (experimental)CRds issued by iA Cores that Hit the LLCCRd_Prefs issued by iA Cores that hit the LLCDRds issued by iA Cores that Hit the LLCDRd PTEs issued by iA Cores that Hit the LLC (experimental)DRd_Prefs issued by iA Cores that Hit the LLCLLCPrefRFO issued by iA Cores that hit the LLCRFOs issued by iA Cores that Hit the LLCRFO_Prefs issued by iA Cores that Hit the LLCSpecItoMs issued by iA Cores that hit in the LLC (experimental)LLCPrefData issued by iA CoresCRd_Prefs issued by iA Cores that Missed the LLCDRd PTEs issued by iA Cores that Missed the LLC (experimental)DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locallyDRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locallyDRd_Prefs issued by iA Cores that Missed the LLCDRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotelyDRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotelyIA_MISS_FULL_STREAMING_WR_DRAMIA_MISS_FULL_STREAMING_WR_LOCAL_DRAMIA_MISS_FULL_STREAMING_WR_REMOTE_DRAMLLCPrefData issued by iA Cores that missed the LLCLLCPrefRFO issued by iA Cores that missed the LLCIA_MISS_PARTIAL_STREAMING_WR_DRAMIA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAMIA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAMWCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory (experimental)RFOs issued by iA Cores that Missed the LLC - HOMed locallyRFO_Prefs issued by iA Cores that Missed the LLCRFO_Prefs issued by iA Cores that Missed the LLC - HOMed locallyRFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotelyRFOs issued by iA Cores that Missed the LLC - HOMed remotelyWBEFtoEs issued by an IA Core.  Non Modified Write Backs (experimental)WBEFtoIs issued by an IA Core.  Non Modified Write Backs (experimental)WBMtoEs issued by an IA Core.  Non Modified Write Backs (experimental)WbMtoIs issued by an iA Cores. Modified Write Backs (experimental)WBStoIs issued by an IA Core.  Non Modified Write Backs (experimental)ItoMs issued by IO Devices that Hit the LLCItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLCPCIRdCurs issued by IO Devices that hit the LLCItoMCacheNears, indicating a partial write request, from IO DevicesItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memoryItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memoryItoMs issued by IO Devices to locally HOMed memoryItoMs issued by IO Devices to remotely HOMed memoryItoMs issued by IO Devices that missed the LLCItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLCFor Transgress 10 (experimental)For Transgress 8 (experimental)For Transgress 9 (experimental)For Transgress 0 (experimental)For Transgress 1 (experimental)For Transgress 2 (experimental)For Transgress 3 (experimental)For Transgress 4 (experimental)For Transgress 5 (experimental)For Transgress 6 (experimental)For Transgress 7 (experimental)Pull Data Partial - Hit LLC (experimental)Pull Data Partial - Hit SF (experimental)RspIFwdPtl Hit LLC (experimental)RspIFwdPtl Hit SF (experimental)Broadcast snoops for Local Requests (experimental)Broadcast snoops for Remote Requests (experimental)Directed snoops for Local Requests (experimental)Directed snoops for Remote Requests (experimental)Snoops sent for Local Requests (experimental)Snoops sent for Remote Requests (experimental)Non UPI AK Request (experimental)Non UPI IV Request (experimental)Acknowledgements to core (experimental)Data Responses to core (experimental)Snoops of processor's cache. (experimental)Acknowledgements to Agent 1 (experimental)Counts the number of times CHA saw NM Set conflict in SF/LLC (experimental)Counts the number of times CHA saw NM Set conflict in TOR (experimental)Remote Rd InvItoE (experimental)RFO HitS Snoop Broadcast (experimental)Number of cycles MBE is high for MS2IDI0 (experimental)Number of cycles MBE is high for MS2IDI1 (experimental)CV0 Prefetch Miss (experimental)CV0 Prefetch Victim (experimental)Silent Snoop Eviction (experimental)Write Combining Aliasing (experimental)Lines in E state (experimental)Local - All Lines (experimental)Local - Lines in E State (experimental)Local - Lines in M State (experimental)Local - Lines in S State (experimental)Lines in M state (experimental)Remote - All Lines (experimental)Remote - Lines in E State (experimental)Remote - Lines in M State (experimental)Remote - Lines in S State (experimental)Lines in S State (experimental)All transactions from Remote Agents (experimental)All Request Filter (experimental)CRd Request Filter (experimental)CRd Requests that come from the local socket (usually the core) (experimental)Code Read Misses (experimental)CRd Requests that come from a Remote socket. (experimental)Local request Filter (experimental)Data Read Request Filter (experimental)Data Read Misses (experimental)Flush or Invalidate Requests (experimental)Flush or Invalidate Requests that come from the local socket (usually the core) (experimental)Flush or Invalidate requests that come from a Remote socket. (experimental)Flush or Invalidate Filter (experimental)Local LLC prefetch requests (from LLC) Filter (experimental)Transactions homed locally Filter (experimental)Transactions homed locally (experimental)Write Request Filter (experimental)Remote non-snoop request Filter (experimental)Locally Requested Reads that are Locally HOMed (experimental)Locally Requested Reads that are Remotely HOMed (experimental)Locally HOMed Read Misses (experimental)Remotely HOMed Read Misses (experimental)READ_OR_SNOOP_REMOTE_MISS_REM_HOMRemotely requested Read or Snoop Misses that are Remotely HOMed (experimental)Remotely Requested Reads that are Locally HOMed (experimental)Reads that Hit the Snoop Filter (experimental)Transactions homed remotely Filter (experimental)Remote snoop request Filter (experimental)Transactions homed remotely (experimental)RFO Request Filter (experimental)RFO Requests that come from the local socket (usually the core) (experimental)RFO Requests that come from a Remote socket. (experimental)SnoopFilter - E State (experimental)SnoopFilter - H State (experimental)SnoopFilter - S State (experimental)Filters Requests for those that write info into the cache (experimental)ISOCH Full Line (experimental)Partial Non-ISOCH (experimental)Deallocate HitME$ on Reads without RspFwdI* (experimental)op is RspIFwd or RspIFwdWb for a local request (experimental)Update HitMe Cache on RdInvOwn even if not RspFwdI* (experimental)op is RspIFwd or RspIFwdWb for a remote request (experimental)Update HitMe Cache to SHARed (experimental)Remote socket RdInvOwn requests that are not to shared line (experimental)Remote socket read or invalidate requests (experimental)Remote socket RdInvOwn requests to shared line (experimental)Remote socket read requests (experimental)Remote socket write (i.e. writeback) requests (experimental)Remote socket ownership read requests that hit in S state. (experimental)Remote socket WBMtoE requests (experimental)Remote socket writeback to I or S requests (experimental)DPT Stalled - IV (experimental)DPT Stalled -  No Credit (experimental)Snoop Not Needed (experimental)Any Cycle with Multiple Snoops (experimental)Any Single Snoop (experimental)Multiple Core Requests (experimental)Single Core Requests (experimental)Multiple Eviction (experimental)Single Eviction (experimental)Multiple External Snoops (experimental)Single External Snoops (experimental)Multiple Snoop Targets from Remote (experimental)Single Snoop Target from Remote (experimental)Intermediate bypass Taken (experimental)[UNC_IMC=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
All DRAM read CAS commands issued (including underfills)Free running counter that increments for the Memory Controller (experimental)DRAM Precharge All Commands (experimental)UNC_M_PARITY_ERRORS (experimental)PMM Read Queue Cycles Full (experimental)PMM Read Queue Cycles Not Empty (experimental)PMM Read Pending Queue OccupancyPMM Write Queue Cycles Full (experimental)PMM Write Queue Cycles Not Empty (experimental)UNC_M_PMM_WPQ_FLUSH (experimental)UNC_M_PMM_WPQ_FLUSH_CYC (experimental)PMM Write Pending Queue OccupancyChannel PPD Cycles (experimental)UNC_M_POWER_CRIT_THROTTLE_CYCLESClock-Enabled Self-Refresh (experimental)Read Data Buffer Full (experimental)Read Data Buffer Inserts (experimental)Read Data Buffer Not Empty (experimental)Read Data Buffer Occupancy (experimental)Read Pending Queue Full Cycles (experimental)Scoreboard Cycles Full (experimental)Scoreboard Cycles Not-Empty (experimental)Number of Scoreboard Requests RejectedThis event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RDThis event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RDThis event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RDWrite Pending Queue Full Cycles (experimental)Miss, existing data may be evicted to Far MemoryWrite Hit in Near Memory CacheNear Mem Read - Clear (experimental)Far Mem Read - Set (experimental)Far Mem Write - Set (experimental)Near Mem Read - Set (experimental)Near Mem Write - Set (experimental)FM requests rejected due to full address conflict (experimental)NM requests rejected due to set conflict (experimental)Patrol requests rejected due to set conflict (experimental)Block region reads (experimental)Block region writes (experimental)Persistent Mem reads (experimental)Persistent Mem writes (experimental)Near Mem Write Starved (experimental)Far Mem Write Starved (experimental)Far Mem Read Starved (experimental)Near Mem Read Starved (experimental)Scoreboard Accesses Accepted (experimental)FM read completions (experimental)FM write completions (experimental)Scoreboard Accesses Rejected (experimental)NM read completions (experimental)NM write completions (experimental)Precharge due to page miss (experimental)Expected No data packet (ERID matched NDP encoding) (experimental)Unexpected No data packet (ERID matched a Read, but data was a NDP) (experimental)Opportunistic Reads (experimental)ERID detectable parity error (experimental)Read Requests - Slot 0 (experimental)Read Requests - Slot 1 (experimental)Misc Commands (error, flow ACKs) (experimental)DRAM RD_CAS commands w/auto-pre (experimental)DRAM WR_CAS commands w/o auto-pre (experimental)DRAM WR_CAS commands w/ auto-pre (experimental)Activate due to Bypass (experimental)[UNC_M2M=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d ext_umask0x%x] %s
Clockticks of the mesh to memory (M2M)UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATECycles when direct to core mode, which bypasses the CHA, was disabled (experimental)UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKEDUNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED (experimental)UNC_M2M_DIRECT2CORE_TXN_OVERRIDENumber of reads in which direct to core transaction was overridden (experimental)UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITSNumber of reads in which direct to Intel UPI transactions were overridden (experimental)UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATECycles when Direct2UPI was Disabled (experimental)UNC_M2M_DIRECT2UPI_TXN_OVERRIDENumber of reads that a message sent direct2 Intel UPI was overridden (experimental)Multi-socket cacheline Directory LookupsMulti-socket cacheline Directory UpdatesUNC_M2M_DISTRESS_PMM (experimental)UNC_M2M_DISTRESS_PMM_MEMMODE (experimental)Write Tracker Inserts (experimental)Write Tracker Occupancy (experimental)UNC_M2M_PREFCAM_CIS_DROPS (experimental)Demands Merged with CAMed PrefetchesUNC_M2M_PREFCAM_DEMAND_NO_MERGEDemands Not Merged with CAMed PrefetchesUNC_M2M_PREFCAM_DROP_REASONS_CH0Data Prefetches Dropped Ch0 - ReasonsUNC_M2M_PREFCAM_DROP_REASONS_CH1Data Prefetches Dropped Ch1 - ReasonsUNC_M2M_PREFCAM_DROP_REASONS_CH2Data Prefetches Dropped Ch2 - ReasonsUNC_M2M_PREFCAM_RxC_CYCLES_NE (experimental)UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHEDUNC_M2M_PREFCAM_RxC_INSERTS (experimental)UNC_M2M_RING_SINK_STARVED_HORZUNC_M2M_RING_SINK_STARVED_VERTM2M to iMC RPQ Cycles w/Credits - RegularM2M->iMC RPQ Cycles w/Credits - PMMM2M to iMC RPQ Cycles w/Credits - SpecialAD Ingress (from CMS) Full (experimental)AD Ingress (from CMS) Not Empty (experimental)AD Ingress (from CMS) Allocations (experimental)AD Ingress (from CMS) Occupancy (experimental)AD Ingress (from CMS) Occupancy - Prefetches (experimental)AK Egress (to CMS) Allocations (experimental)BL Ingress (from CMS) Full (experimental)BL Ingress (from CMS) Not Empty (experimental)BL Ingress (from CMS) Allocations (experimental)BL Ingress (from CMS) Occupancy (experimental)UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTSUNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS (experimental)UNC_M2M_SCOREBOARD_AD_RETRY_REJECTSUNC_M2M_SCOREBOARD_AD_RETRY_REJECTS (experimental)UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTSRetry - Mem Mirroring Mode (experimental)UNC_M2M_SCOREBOARD_BL_RETRY_REJECTSScoreboard Accepts (experimental)Scoreboard Rejects (experimental)UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1Number AD Ingress Credits (experimental)Number BL Ingress Credits (experimental)UNC_M2M_TxC_AD_CREDITS_ACQUIREDAD Egress (to CMS) Credit Acquired (experimental)UNC_M2M_TxC_AD_CREDIT_OCCUPANCYAD Egress (to CMS) Credits Occupancy (experimental)AD Egress (to CMS) Full (experimental)AD Egress (to CMS) Not Empty (experimental)AD Egress (to CMS) Allocations (experimental)UNC_M2M_TxC_AD_NO_CREDIT_CYCLESCycles with No AD Egress (to CMS) Credits (experimental)UNC_M2M_TxC_AD_NO_CREDIT_STALLEDCycles Stalled with No AD Egress (to CMS) Credits (experimental)AD Egress (to CMS) Occupancy (experimental)UNC_M2M_TxC_AK_CREDITS_ACQUIREDAK Egress (to CMS) Credit AcquiredAK Egress (to CMS) AllocationsUNC_M2M_TxC_AK_NO_CREDIT_CYCLESCycles with No AK Egress (to CMS) CreditsUNC_M2M_TxC_AK_NO_CREDIT_STALLEDCycles Stalled with No AK Egress (to CMS) CreditsUNC_M2M_TxC_BL_CREDITS_ACQUIREDBL Egress (to CMS) Credit AcquiredBL Egress (to CMS) AllocationsUNC_M2M_TxC_BL_NO_CREDIT_CYCLESCycles with No BL Egress (to CMS) CreditsUNC_M2M_TxC_BL_NO_CREDIT_STALLEDCycles Stalled with No BL Egress (to CMS) CreditsM2M->iMC WPQ Cycles w/Credits - RegularM2M->iMC WPQ Cycles w/Credits - PMMM2M->iMC WPQ Cycles w/Credits - SpecialWrite Tracker Cycles Not EmptyUNC_M2M_WR_TRACKER_NONPOSTED_INSERTSWrite Tracker Non-Posted InsertsUNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCYWrite Tracker Non-Posted OccupancyUNC_M2M_WR_TRACKER_POSTED_INSERTSUNC_M2M_WR_TRACKER_POSTED_OCCUPANCYWrite Tracker Posted OccupancyCommon Mesh Stop - Near Side (experimental)Common Mesh Stop - Far Side (experimental)CRD Transactions to Cbo (experimental)NDR Transactions (experimental)Clean NearMem Underfill Hit (experimental)Dirty NearMem Underfill Hit (experimental)UPI - All Channels (experimental)XPT - All Channels (experimental)XPT & UPI - Ch 0 (experimental)XPT & UPI - Ch 1 (experimental)XPT & UPI - Ch 2 (experimental)XPT & UPI - All Channels (experimental)XPT & UPI- Ch 0 (experimental)XPT & UPI- Ch 2 (experimental)XPT & UPI- All Channels (experimental)All Writes - All Channels (experimental)All Writes - Ch0 (experimental)Full Line Non-ISOCH - Ch0 (experimental)ISOCH Full Line - Ch0 (experimental)Non-Inclusive - Ch0 (experimental)Non-Inclusive Miss - Ch0 (experimental)Partial Non-ISOCH - Ch0 (experimental)ISOCH Partial - Ch0 (experimental)DDR, acting as Cache - Ch0 (experimental)All Writes - Ch1 (experimental)Full Line Non-ISOCH - Ch1 (experimental)ISOCH Full Line - Ch1 (experimental)Non-Inclusive - Ch1 (experimental)Non-Inclusive Miss - Ch1 (experimental)Partial Non-ISOCH - Ch1 (experimental)ISOCH Partial - Ch1 (experimental)DDR, acting as Cache - Ch1 (experimental)From TGR - All Channels (experimental)Full Line Non-ISOCH - All Channels (experimental)ISOCH Full Line - All Channels (experimental)Non-Inclusive - All Channels (experimental)Non-Inclusive Miss - All Channels (experimental)Partial Non-ISOCH - All Channels (experimental)ISOCH Partial - All Channels (experimental)DDR, acting as Cache - All Channels (experimental)DDR - All Channels (experimental)All, regardless of priority. - All Channels (experimental)All, regardless of priority. - Ch0 (experimental)Critical Priority - Ch0 (experimental)Normal Priority - Ch0 (experimental)All, regardless of priority. - Ch1 (experimental)Critical Priority - Ch1 (experimental)Normal Priority - Ch1 (experimental)Critical Priority - All Channels (experimental)Normal Priority - All Channels (experimental)From/to any state. Note: event counts are incorrect in 2LM mode.On NonDirty Line in A State (experimental)On NonDirty Line in I State (experimental)On NonDirty Line in L State (experimental)On NonDirty Line in S State (experimental)On Dirty Line in A State (experimental)On Dirty Line in I State (experimental)On Dirty Line in L State (experimental)On Dirty Line in S State (experimental)[UNC_IIO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d fc_mask=%d ch_mask=%d] %s
Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOCClockticks of the integrated IO (IIO) traffic controllerFree running counter that increments for IIO clocktickPCIe Completion Buffer Occupancy of completions with dataFour byte data request of the CPUIncoming arbitration requests grantedCounting disabled (experimental)UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPUOccupancy of outbound request queueUNC_IIO_NUM_OUTSTANDING_REQ_OF_CPUNumber requests sent to PCIe from main dieNumber requests PCIe makes of the main dieNum requests sent by PCIe - by targetUNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPUITC address map 1 (experimental)UNC_IIO_OUTBOUND_CL_REQS_ISSUEDOutbound cacheline requests issuedUNC_IIO_OUTBOUND_TLP_REQS_ISSUEDOutbound TLP (transaction layer packet) requests issuedPCIe Request - cacheline completeUNC_IIO_REQ_FROM_PCIE_PASS_CMPLSymbol Times on Link (experimental)Number Transactions requested by the CPUNumber Transactions requested of the CPUAtomic requests targeting DRAM (experimental)CmpD - device sending completion to CPU request (experimental)CmpD - device sending completion to CPU requestCard reading from DRAM (experimental)Card writing to DRAM (experimental)Card reading from another Card (same or different stack) (experimental)Card writing to another Card (same or different stack) (experimental)Core reading from Card's PCICFG space (experimental)Core writing to Card's PCICFG space (experimental)Core reading from Card's IO space (experimental)Core writing to Card's IO space (experimental)Core reading from Card's MMIO space (experimental)Core reading from Card's MMIO spaceCore writing to Card's MMIO space (experimental)Core writing to Card's MMIO spaceAnother card (different IIO stack) reading from this card. (experimental)Another card (different IIO stack) writing to this card. (experimental)Passing data to be written (experimental)Issuing final read or write of line (experimental)Request Ownership (experimental)Processing response from IOMMU (experimental)Issuing to IOMMU (experimental)64B requests issued to device (experimental)Completion allocations (experimental)Non-PCIE bus and PCIE bus (experimental)Non-PCIE bus and !(PCIE bus) (experimental)!(Non-PCIE bus) and PCIE bus (experimental)!(Non-PCIE bus) and !(PCIE bus) (experimental)Interrupt Entry cache hit (experimental)Interrupt Entry cache lookup (experimental)Device-selective Context cache invalidation cycles (experimental)Domain-selective Context cache invalidation cycles (experimental)Context cache global invalidation cycles (experimental)Domain-selective IOTLB invalidation cycles (experimental)Global IOTLB invalidation cycles (experimental)Page-selective IOTLB invalidation cycles (experimental)Cycles PWT full (experimental)IOMMU memory access (experimental)PWC Hit to a 1G page (experimental)PWC Hit to a 2M page (experimental)PWC Hit to a 4K page (experimental)PWT Hit to a 256T page (experimental)PageWalk cache fill (experimental)PageWalk cache lookup (experimental)IOTLB Hits to a 1G Page (experimental)IOTLB Hits to a 2M Page (experimental)IOTLB Hits to a 4K Page (experimental)IOTLB lookups all (experimental)Context cache hits (experimental)Context cache lookups (experimental)IOTLB lookups first (experimental)IOTLB Fills (same as IOTLB miss) (experimental)Core reporting completion of Card read from Core DRAM (experimental)Core reporting completion of Card read from Core DRAM[UNC_IRP=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d fc_mask=%d ch_mask=%d] %s
Total IRP occupancy of inbound read and write requests to coherent memory.Clockticks of the IO coherency tracker (IRP)PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.Inbound read requests received by the IRP and inserted into the FAF queue.Occupancy of the IRP FAF queue.Responses to snoops of any type that hit M line in the IIO cacheInbound write (fast path) requests received by the IRP.AK Egress Allocations (experimental)BL DRS Egress Cycles Full (experimental)BL DRS Egress Inserts (experimental)BL DRS Egress Occupancy (experimental)BL NCB Egress Cycles Full (experimental)BL NCB Egress Inserts (experimental)BL NCB Egress Occupancy (experimental)BL NCS Egress Cycles Full (experimental)BL NCS Egress Inserts (experimental)BL NCS Egress Occupancy (experimental)UNC_I_TxR2_AD01_STALL_CREDIT_CYCLESUNC_I_TxR2_AD01_STALL_CREDIT_CYCLES (experimental)UNC_I_TxR2_AD0_STALL_CREDIT_CYCLESNo AD0 Egress Credits Stalls (experimental)UNC_I_TxR2_AD1_STALL_CREDIT_CYCLESNo AD1 Egress Credits Stalls (experimental)UNC_I_TxR2_BL_STALL_CREDIT_CYCLESNo BL Egress Credit Stalls (experimental)Outbound Read Requests (experimental)Outbound Request Queue Occupancy (experimental)P2P completions (experimental)match if local only (experimental)match if local and target matches (experimental)Match if remote only (experimental)match if remote and target matches (experimental)Received Invalid (experimental)Slow Transfer of E Line (experimental)Slow Transfer of I Line (experimental)Slow Transfer of M Line (experimental)Slow Transfer of S Line (experimental)Cache Inserts of Atomic Transactions as Secondary (experimental)Cache Inserts of Read Transactions as Secondary (experimental)Cache Inserts of Write Transactions as Secondary (experimental)Fastpath Rejects (experimental)Fastpath Requests (experimental)Fastpath Transfers From Primary to Secondary (experimental)Prefetch Ack Hints From Primary to Secondary (experimental)Slow path fwpf didn't find prefetch (experimental)All Inserts Outbound (BL, AK, Snoops) (experimental)All Inserts Inbound (p2p + faf + cset)[UNC_PCU=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d tid_en=%d occ_inv=%d occ_edge=%d] %s
Clockticks of the power control unit (PCU)UNC_P_CORE_TRANSITION_CYCLES (experimental)UNC_P_DEMOTIONS (experimental)Phase Shed 0 Cycles (experimental)Phase Shed 1 Cycles (experimental)Phase Shed 2 Cycles (experimental)Phase Shed 3 Cycles (experimental)AVX256 Frequency Clipping (experimental)AVX512 Frequency Clipping (experimental)Thermal Strongest Upper Limit Cycles (experimental)Power Strongest Upper Limit Cycles (experimental)IO P Limit Strongest Lower Limit Cycles (experimental)Cycles spent changing Frequency (experimental)Memory Phase Shedding Cycles (experimental)Package C State Residency - C0 (experimental)Package C State Residency - C2E (experimental)Package C State Residency - C3 (experimental)Package C State Residency - C6 (experimental)UNC_P_PMAX_THROTTLED_CYCLES (experimental)External Prochot (experimental)Internal Prochot (experimental)Total Core C State Transition Cycles (experimental)[UNC_UPI=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2UNC_UPI_M3_CRD_RETURN_BLOCKED (experimental)UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2Cycles where phy is not in L0, L0c, L0p, L1 (experimental)L1 Req (same as L1 Ack). (experimental)Matches on Receive path of a UPI PortCRC Errors Detected (experimental)UNC_UPI_RxL_CRC_LLR_REQ_TRANSMITLLR Requests Sent (experimental)UNC_UPI_RxL_CREDITS_CONSUMED_VN0VN0 Credit Consumed (experimental)UNC_UPI_RxL_CREDITS_CONSUMED_VN1VN1 Credit Consumed (experimental)UNC_UPI_RxL_CREDITS_CONSUMED_VNAVNA Credit Consumed (experimental)UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTLUNC_UPI_TxL0P_POWER_CYCLES_LL_ENTERUNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER (experimental)UNC_UPI_TxL0P_POWER_CYCLES_M3_EXITUNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT (experimental)Matches on Transmit path of a UPI PortTx Flit Buffer Bypassed (experimental)Tx Flit Buffer Allocations (experimental)Tx Flit Buffer Occupancy (experimental)UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01 (experimental)VNA Credits Pending Return - Occupancy (experimental)Null FLITs transmitted to any slotLLCRD Not Empty (experimental)Slot NULL or LLCRD Empty (experimental)Protocol Header (experimental)Non-Coherent Bypass (experimental)Non-Coherent Bypass, Match Opcode (experimental)Non-Coherent Standard (experimental)Non-Coherent Standard, Match Opcode (experimental)Request, Match Opcode (experimental)Response - Conflict (experimental)Response - Invalid (experimental)Response - Data (experimental)Response - Data, Match Opcode (experimental)Response - No Data (experimental)Response - No Data, Match Opcode (experimental)Snoop, Match Opcode (experimental)Writeback, Match Opcode (experimental)Null FLITs received from any slotNull FLITs received from any slot (experimental)UNC_M3UPI_AG0_AD_CRD_ACQUIRED0UNC_M3UPI_AG0_AD_CRD_ACQUIRED1UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1UNC_M3UPI_AG0_BL_CRD_ACQUIRED0UNC_M3UPI_AG0_BL_CRD_ACQUIRED1UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1UNC_M3UPI_AG1_AD_CRD_ACQUIRED0UNC_M3UPI_AG1_AD_CRD_ACQUIRED1UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1UNC_M3UPI_AG1_BL_CRD_ACQUIRED0UNC_M3UPI_AG1_BL_CRD_ACQUIRED1UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1UNC_M3UPI_CHA_AD_CREDITS_EMPTYClockticks of the mesh to UPI (M3UPI)UNC_M3UPI_HORZ_RING_AKC_IN_USEUNC_M3UPI_RING_SINK_STARVED_HORZUNC_M3UPI_RING_SINK_STARVED_VERTVN0 Ingress (from CMS) Queue - Cycles Not EmptyVN1 Ingress (from CMS) Queue - Cycles Not EmptyUNC_M3UPI_RxC_DATA_FLITS_NOT_SENTGenerating BL Data Flit SequenceUNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVEDSlotting BL Message Into Header FlitUNC_M3UPI_RxC_HDR_FLIT_NOT_SENTVN0 Ingress (from CMS) Queue - InsertsVN1 Ingress (from CMS) Queue - InsertsVN0 Ingress (from CMS) Queue - OccupancyVN1 Ingress (from CMS) Queue - OccupancyUNC_M3UPI_RxC_PACKING_MISS_VN0VN0 message can't slot into flitUNC_M3UPI_RxC_PACKING_MISS_VN1VN1 message can't slot into flitUNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1UNC_M3UPI_TxC_AD_FLQ_CYCLES_NEUNC_M3UPI_TxC_AD_FLQ_OCCUPANCYAK Flow Q Inserts (experimental)UNC_M3UPI_TxC_AK_FLQ_OCCUPANCYAK Flow Q Occupancy (experimental)UNC_M3UPI_TxC_BL_FLQ_CYCLES_NEUNC_M3UPI_TxC_BL_FLQ_OCCUPANCYUNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCYUNC_M3UPI_TxR_HORZ_CYCLES_FULLUNC_M3UPI_TxR_VERT_CYCLES_FULL0UNC_M3UPI_TxR_VERT_CYCLES_FULL1UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTYUNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTYFlowQ Generated Prefetch (experimental)UNC_M3UPI_VERT_RING_AKC_IN_USEUNC_M3UPI_VERT_RING_TGC_IN_USEUNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0UNC_M3UPI_WB_PENDING.LOCALDEST_VN0BOTHNONZERO_RT_EQ_LOCALDEST_VN0BOTHNONZERO_RT_EQ_LOCALDEST_VN1BOTHNONZERO_RT_GT_LOCALDEST_VN0BOTHNONZERO_RT_GT_LOCALDEST_VN1BOTHNONZERO_RT_LT_LOCALDEST_VN0BOTHNONZERO_RT_LT_LOCALDEST_VN1VN0 RSP Messages (experimental)VN0 REQ Messages (experimental)VN0 SNP Messages (experimental)VN1 RSP Messages (experimental)VN1 REQ Messages (experimental)VN1 SNP Messages (experimental)VN0 WB Messages (experimental)VN0 NCB Messages (experimental)VN1 WB Messages (experimental)VN1_NCS Messages (experimental)VN0 NCS Messages (experimental)VN1_NCB Messages (experimental)VN1 NCS Messages (experimental)VN1 NCB Messages (experimental)Parallel Attempt (experimental)Parallel Success (experimental)No BGF Credits + No Extra Message Slotted (experimental)No TxQ Credits + No Extra Message Slotted (experimental)Cycle valid for Flit (experimental)One Message in non-VNA (experimental)Two Slots Taken (experimental)All Slots Taken (experimental)Parallel Flit Finished (experimental)Parallel Message (experimental)Rate-matching Stall (experimental)Rate-matching Stall - No Message (experimental)Accumulate Ready (experimental)Accumulate Wasted (experimental)Run-Ahead - Blocked (experimental)Run-Ahead - Message (experimental)Needs Data Flit (experimental)Don't Need Pump 1 (experimental)Don't Need Pump 1 - Bubble (experimental)Don't Need Pump 1 - Not Avail (experimental)Credits Consumed (experimental)Packets in BGF FIFO (experimental)Packets in BGF Path (experimental)Transmit Credits (experimental)Any In BGF FIFO (experimental)Any in BGF Path (experimental)AD to Slot 0 on BL Arb (experimental)AD to Slot 0 on Idle (experimental)AD + BL to Slot 1 (experimental)AD + BL to Slot 2 (experimental)AD, BL Parallel Win VN0 (experimental)AD, BL Parallel Win VN1 (experimental)Max Parallel Win (experimental)No Progress on Pending AD VN0 (experimental)No Progress on Pending AD VN1 (experimental)No Progress on Pending BL VN0 (experimental)No Progress on Pending BL VN1 (experimental)VN0, VN1 Parallel Win (experimental)IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) (experimental)All IIO targets for NCS are in single mask. ORs them together (experimental)Selected M2p BL NCS credits (experimental)[UNC_UBOX=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
Clockticks in the UBOX using a dedicated 48-bit Fixed CounterIDI Lock/SplitLock Cycles (experimental)[UNC_M2PCIE=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s
Clockticks of the mesh to PCI (M2P)M2PCIe IIO Failed to Acquire a CreditUNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0Local Dedicated P2P Credit Taken - 0UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1Local Dedicated P2P Credit Taken - 1UNC_M2P_LOCAL_P2P_DED_RETURNED_0Local P2P Dedicated Credits Returned - 0UNC_M2P_LOCAL_P2P_DED_RETURNED_1Local P2P Dedicated Credits Returned - 1UNC_M2P_LOCAL_P2P_SHAR_RETURNEDLocal P2P Shared Credits ReturnedUNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNEDLocal Shared P2P Credit Returned to credit ringUNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0Local Shared P2P Credit Taken - 0UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1Local Shared P2P Credit Taken - 1UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0Waiting on Local Shared P2P Credit - 0UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1Waiting on Local Shared P2P Credit - 1UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0Remote Dedicated P2P Credit Taken - 0UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1Remote Dedicated P2P Credit Taken - 1UNC_M2P_REMOTE_P2P_DED_RETURNEDRemote P2P Dedicated Credits ReturnedUNC_M2P_REMOTE_P2P_SHAR_RETURNEDRemote P2P Shared Credits ReturnedUNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNEDRemote Shared P2P Credit Returned to credit ringUNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0Remote Shared P2P Credit Taken - 0UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1Remote Shared P2P Credit Taken - 1UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0Waiting on Remote Shared P2P Credit - 0UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1Waiting on Remote Shared P2P Credit - 1UNC_M2P_RING_SINK_STARVED_HORZUNC_M2P_RING_SINK_STARVED_VERTIngress (from CMS) Queue Cycles Not EmptyIngress (from CMS) Queue InsertsUNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1Egress (to CMS) Cycles Not EmptyDRS to CMS Port 0 (experimental)DRS to CMS Port 1 (experimental)NCB to CMS Port 0 (experimental)NCB to CMS Port 1 (experimental)NCS to CMS Port 0 (experimental)NCS to CMS Port 1 (experimental)Intel SapphireRapids IMC11 uncoreIntel SapphireRapids IMC10 uncoreIntel SapphireRapids IMC9 uncoreIntel SapphireRapids IMC8 uncoreIntel SapphireRapids IMC7 uncoreIntel SapphireRapids IMC6 uncoreIntel SapphireRapids IMC5 uncoreIntel SapphireRapids IMC4 uncoreIntel SapphireRapids IMC3 uncoreIntel SapphireRapids IMC2 uncoreIntel SapphireRapids IMC1 uncoreIntel SapphireRapids IMC0 uncoreCAS Command in Regular Mode issuedIMC Clockticks at DCLK frequencyIMC Clockticks at HCLK frequencyPMM Read Pending Queue insertsPMM Read Pending Queue occupancyPMM (for IXP) Write Queue Cycles Not Empty (experimental)PMM Write Pending Queue insertsCount number of DRAM PrechargeCounts the number of cycles where the read buffer has greater than UMASK elements.  This includes reads to both DDR and PMEM.  NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR). (experimental)Counts the number of cycles where there is at least one element in the read buffer.  This includes reads to both DDR and PMEM.Counts the number of elements in the read buffer, including reads to both DDR and PMEM. (experimental)Read Pending Queue Occupancy pseudo-channel 0Write Pending Queue Occupancy pseudo channel 0Write Pending Queue Occupancy pseudo channel 1Write Pending Queue CAM Match (experimental)2LM Tag check hit in near memory cache (DDR4)2LM Tag check miss, no data at this line2LM Tag check miss, existing data may be evicted to PMM2LM Tag check hit due to memory read2LM Tag check hit due to memory writeNumber of Scoreboard Requests Rejected (experimental)Scoreboard accepts (experimental)Scoreboard rejects (experimental)Pseudo-channel 0 (experimental)Pseudo-channel 1 (experimental)Read Data Buffer Not Empty any channel (experimental)Precharge due to read, write, underfill, or PGT.Precharges from Page Table (experimental)DRAM Precharge commands. (experimental)Precharge due to read on page missPrecharge due to read (experimental)Precharge due to write on page missPrecharge due to write (experimental)Throttle Cycles for Rank 0 (experimental)PMM (for IXP) Write Pending Queue Occupancy (experimental)PMM Read Pending Queue Occupancy (experimental)Pseudo Channel 0 (experimental)Pseudo Channel 1 (experimental)Read CAS Command in Interleaved Mode (32B) (experimental)Read CAS Command in Regular Mode (64B) in Pseudochannel 0 (experimental)Underfill Read CAS Command in Interleaved Mode (32B) (experimental)Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1 (experimental)Write CAS Command in Interleaved Mode (32B) (experimental)Write CAS Command in Regular Mode (64B) in Pseudochannel 0 (experimental)DRAM RD_CAS and WR_CAS Commands. (experimental)All DRAM read CAS commands issued (does not include underfills) (experimental)DRAM underfill read CAS commands issued (experimental)All DRAM write CAS commands issuedActivate due to read, write, underfill, or bypassIntel SapphireRapids UPI3 uncoreIntel SapphireRapids UPI2 uncoreIntel SapphireRapids UPI1 uncoreIntel SapphireRapids UPI0 uncoreReceive Flit Buffer AllocationsTransmitted Flit Buffer Bypassed (experimental)Transmitted Flit Buffer Allocations (experimental)Transmitted Flit Buffer Occupancy (experimental)All LLCRD Not Empty (experimental)All Protocol Header (experimental)Intel SapphireRapids CHA59 uncoreIntel SapphireRapids CHA58 uncoreIntel SapphireRapids CHA57 uncoreIntel SapphireRapids CHA56 uncoreIntel SapphireRapids CHA55 uncoreIntel SapphireRapids CHA54 uncoreIntel SapphireRapids CHA53 uncoreIntel SapphireRapids CHA52 uncoreIntel SapphireRapids CHA51 uncoreIntel SapphireRapids CHA50 uncoreIntel SapphireRapids CHA49 uncoreIntel SapphireRapids CHA48 uncoreIntel SapphireRapids CHA47 uncoreIntel SapphireRapids CHA46 uncoreIntel SapphireRapids CHA45 uncoreIntel SapphireRapids CHA44 uncoreIntel SapphireRapids CHA43 uncoreIntel SapphireRapids CHA42 uncoreIntel SapphireRapids CHA41 uncoreIntel SapphireRapids CHA40 uncoreIntel SapphireRapids CHA39 uncoreIntel SapphireRapids CHA38 uncoreIntel SapphireRapids CHA37 uncoreIntel SapphireRapids CHA36 uncoreIntel SapphireRapids CHA35 uncoreIntel SapphireRapids CHA34 uncoreIntel SapphireRapids CHA33 uncoreIntel SapphireRapids CHA32 uncoreIntel SapphireRapids CHA31 uncoreIntel SapphireRapids CHA30 uncoreIntel SapphireRapids CHA29 uncoreIntel SapphireRapids CHA28 uncoreIntel SapphireRapids CHA27 uncoreIntel SapphireRapids CHA26 uncoreIntel SapphireRapids CHA25 uncoreIntel SapphireRapids CHA24 uncoreIntel SapphireRapids CHA23 uncoreIntel SapphireRapids CHA22 uncoreIntel SapphireRapids CHA21 uncoreIntel SapphireRapids CHA20 uncoreIntel SapphireRapids CHA19 uncoreIntel SapphireRapids CHA18 uncoreIntel SapphireRapids CHA17 uncoreIntel SapphireRapids CHA16 uncoreIntel SapphireRapids CHA15 uncoreIntel SapphireRapids CHA14 uncoreIntel SapphireRapids CHA13 uncoreIntel SapphireRapids CHA12 uncoreIntel SapphireRapids CHA11 uncoreIntel SapphireRapids CHA10 uncoreIntel SapphireRapids CHA9 uncoreIntel SapphireRapids CHA8 uncoreIntel SapphireRapids CHA7 uncoreIntel SapphireRapids CHA6 uncoreIntel SapphireRapids CHA5 uncoreIntel SapphireRapids CHA4 uncoreIntel SapphireRapids CHA3 uncoreIntel SapphireRapids CHA2 uncoreIntel SapphireRapids CHA1 uncoreIntel SapphireRapids CHA0 uncoreMulti-socket cacheline Directory state lookupsMulti-socket cacheline Directory state updatesMemory controller reads from CHAMemory controller writes from CHAIngress (from CMS) Request Queue RejectsCLFlushOpt from Local IA (experimental)Rd Pref from local IA (experimental)DRd Opt from local IA (experimental)DRd Opt Pref from local IA (experimental)All requests issued from IA cores to CXL accelerator memory regions that hit the LLC. (experimental)DRd Opt hits from local IA (experimental)DRd Opt Pref hits from local IA (experimental)LLCPrefCode hits from local IA (experimental)LLCPrefData hits from local IA (experimental)ItoM from Local IA (experimental)LLCPrefCode from local IA (experimental)CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator. (experimental)All requests issued from IA cores to CXL accelerator memory regions that miss the LLC. (experimental)DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator. (experimental)DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card. (experimental)DRds issued by IA Cores targeting DDR Mem that Missed the LLCDRd misses from local IA targeting local memoryDRd Opt misses from local IA (experimental)DRd Opt Pref misses from local IA (experimental)IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCALL2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator. (experimental)IA_MISS_DRD_PREF_CXL_ACC_LOCALDRd Pref misses from local IA targeting local memoryDRd Pref misses from local IA targeting remote memoryDRd misses from local IA targeting remote memoryLLCPrefCode misses from local IA (experimental)LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator. (experimental)LLCPrefData misses from local IALLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator. (experimental)IA_MISS_LLCPREFDATA_CXL_ACC_LOCALLLCPrefRFO misses from local IAIA_MISS_LLCPREFRFO_CXL_ACC_LOCALRFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator. (experimental)RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator. (experimental)LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator. (experimental)IA_MISS_RFO_PREF_CXL_ACC_LOCALRFO prefetch misses from local IACLFlushes issued by IO DevicesRdCur and FsRdCur hits from local IOItoMCacheNears from IO devices.RdCur and FsRdCur misses from local IONot Near Memory (experimental)All from Remote (experimental)All Snoops from Remote (experimental)RspI Snoop Responses Received (experimental)RspIFwd Snoop Responses Received (experimental)RspS Snoop Responses Received (experimental)RspSFwd Snoop Responses Received (experimental)Broadcast snoop for Local Requests (experimental)Broadcast or directed Snoops sent for Local Requests (experimental)Broadcast or directed Snoops sent for Remote Requests (experimental)Ingress (from CMS) Request Queue Rejects; PhyAddr Match (experimental)Requests for exclusive ownership of a cache line without receiving data (experimental)Local requests for exclusive ownership of a cache line  without receiving dataRemote requests for exclusive ownership of a cache line  without receiving dataRead requests made into the CHARead requests from a unit on this socketRead requests from a remote socketWrite requests made into the CHAWrite Requests from a unit on this socketRead and Write Requests; Writes RemoteNumber of SLOW TOR Request inserted to ha_pmm_tor_req_fifo (experimental)Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in SF/LLC (experimental)Memory Mode related events; Counts the number of times CHA saw a Near memory set conflict in SF/LLC (experimental)Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in TOR (experimental)Number of times that an RFO hit in S state. (experimental)All LLC lines in E state that are victimized on a fill from an IO device (experimental)All LLC lines in F or S state that are victimized on a fill from an IO device (experimental)All LLC lines in M state that are victimized on a fill from an IO device (experimental)All LLC lines in any state that are victimized on a fill from an IO device (experimental)Lines Victimized; Local - All Lines (experimental)Lines Victimized (experimental)Lines Victimized; Remote - All Lines (experimental)All LLC lines in E state that are victimized on a fill (experimental)All LLC lines in M state that are victimized on a fill (experimental)All LLC lines in S state that are victimized on a fill (experimental)Cache and Snoop Filter Lookups; Any Request (experimental)Local non-prefetch requests (experimental)Cache and Snoop Filter Lookups; Data Read Request (experimental)Demand Data Reads, Core and LLC prefetches (experimental)Local LLC prefetch requests (from LLC) (experimental)Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core) (experimental)Demand CRd Requests that come from the local socket (usually the core) (experimental)Cache and Snoop Filter Lookups; Demand Data Reads that come from the local socket (usually the core) (experimental)Demand RFO Requests that come from the local socket (usually the core) (experimental)Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core) (experimental)Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core) (experimental)CRd Prefetches that come from the local socket (usually the core) (experimental)RFO Prefetches that come from the local socket (usually the core) (experimental)Remote non-snoop requests (experimental)Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket (experimental)Filters Requests for those that write info into the cache that come from a remote socket (experimental)Remote snoop requests (experimental)Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket (experimental)Locally HOMed RFOs - Demand and Prefetches (experimental)CHA to iMC Full Line Writes Issued; Full Line Non-ISOCHNo SF/LLC HitS/F and op is RdInvOwn (experimental)Op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv* (experimental)SF/LLC HitS/F and op is RdInvOwn (experimental)Op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv* (experimental)Op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS (experimental)Read request from a remote socket which hit in the HitMe Cache to a line In the E state (experimental)Shared hit and op is RdInvOwn, RdInv, Inv* (experimental)Op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS (experimental)Directory Updated memory write from the HA pipeDirectory Updated memory write from TOR pipeIntel GraniteRapids IMC11 uncoreIntel GraniteRapids IMC10 uncoreIntel GraniteRapids IMC9 uncoreIntel GraniteRapids IMC8 uncoreIntel GraniteRapids IMC7 uncoreIntel GraniteRapids IMC6 uncoreIntel GraniteRapids IMC5 uncoreIntel GraniteRapids IMC4 uncoreIntel GraniteRapids IMC3 uncoreIntel GraniteRapids IMC2 uncoreIntel GraniteRapids IMC1 uncoreIntel GraniteRapids IMC0 uncoreCAS count for SubChannel 0 regular readsCAS count for SubChannel 1 regular readsNumber of DRAM DCLK clock cycles while the event is enabled.  DCLK is 1/4 of DRAM data rate.Number of DRAM HCLK clock cycles while the event is enabled (experimental)Number of cycles a given rank is in Power Down ModeUNC_M_POWER_CHANNEL_PPD_CYCLESNumber of cycles a given rank is in Power Down Mode and all pages are closed (experimental)Read buffer inserts on subchannel 0Read buffer occupancy on subchannel 0Read buffer occupancy on subchannel 1Read Pending Queue inserts for subchannel 0, pseudochannel 0Read pending queue occupancy for subchannel 0, pseudochannel 0Read pending queue occupancy for subchannel 0, pseudochannel 1Read pending queue occupancy for subchannel 1, pseudochannel 0Read pending queue occupancy for subchannel 1, pseudochannel 1Number of cycles all ranks were in SRWrite Pending Queue inserts for subchannel 0, pseudochannel 0Write pending queue occupancy for subchannel 0, pseudochannel 0Write pending queue occupancy for subchannel 0, pseudochannel 1Write pending queue occupancy for subchannel 1, pseudochannel 0Write pending queue occupancy for subchannel 1, pseudochannel 1Write Pending Queue Allocations (experimental)Write Pending Queue inserts for subchannel 0, pseudochannel 1Write Pending Queue inserts for subchannel 1, pseudochannel 0Write Pending Queue inserts for subchannel 1, pseudochannel 1Number of cycles all ranks were in SR subevent1 - # of times all ranks went into SR subevent2 -# of times  ps_sr_active asserted (SRE) subevent3 - # of times ps_sr_active deasserted (SRX) subevent4 - # of times PS-&>Refresh ps_sr_req asserted (SRE) subevent5 - # of times PS-&>Refresh ps_sr_req deasserted (SRX) subevent6 - # of cycles PSCtrlr FSM was in FATAL (experimental)Number of cycles all ranks were in SR (experimental)Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests. (experimental)Read Pending Queue inserts for subchannel 0, pseudochannel 1Read Pending Queue inserts for subchannel 1, pseudochannel 0Read Pending Queue inserts for subchannel 1, pseudochannel 1Read buffer inserts on subchannel 1Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.Counts the number of DRAM Precharge commands sent on this channel. (experimental)Number of cycles a given rank is in Power Down Mode (experimental)CAS count for SubChannel 1, all CAS operationsCAS count for SubChannel 1, all readsCAS count for SubChannel 1 underfill readsCAS count for SubChannel 1, all writesCAS count for SubChannel 1 regular writes (experimental)CAS count for SubChannel 1 auto-precharge writes (experimental)CAS count for SubChannel 0, all CAS operationsCAS count for SubChannel 0, all readsCAS count for SubChannel 0 underfill readsCAS count for SubChannel 0, all writesCAS count for SubChannel 0 regular writes (experimental)CAS count for SubChannel 0 auto-precharge writes (experimental)Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates. (experimental)Underfill Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates. (experimental)Write transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates. (experimental)Number of actual bank conflictsNumber of taken and not taken branches, including: conditional branches, jumps, calls, returns, software interrupts, and interrupt returnsNumber of branch mispredictions that occurred on BTB hits. BTB misses are not considered branch mispredicts because no prediction exists for them yet.Number of instruction reads that miss the internal code cache; whether the read is cacheable or noncacheableNumber of instruction reads; whether the read is cacheable or noncacheableNumber of cycles during which the processor is not halted.Number of dirty lines (all) that are written back, regardless of the causeNumber of successful memory data reads committed by the K-unit (L1). Cache accesses resulting from prefetch instructions are included for A0 stepping.Number of memory read accesses that miss the internal data cache whether or not the access is cacheable or noncacheable. Cache accesses resulting from prefetch instructions are not included.Number of memory read and/or write accesses that miss the internal data cache, whether or not the access is cacheable or noncacheableNumber of memory data reads and/or writes (internal data cache hit and miss combined). Read cache accesses resulting from prefetch instructions are included for A0 stepping.Number of successful memory data writes committed by the K-unit (L1). Streaming stores (hit/miss L1), cacheable write partials, and UC promotions are all included.Number of memory write accesses that miss the internal data cache whether or not the access is cacheable. Non-cacheable misses are not included.Number of E-stage cycles that were successfully completed. Includes cycles generated by multi-cycle E-stage instructions. For instructions destined for the FPU or VPU pipelines, this event only counts occupancy in the integer E-stage.Number of cycles where the front-end could not advance. Any multi-cycle instructions which delay pipeline advance and apply backpressure to the front-end will be included, e.g. read-modify-write instructions. Includes cycles when the front-end did not have any instructions to issue.Number of instructions executed (up to two per clock)Number of instructions executed in the V_pipe. The event indicates the number of instructions that were paired.Number of data requests which hit an in-flight vprefetch0. The in-flight vprefetch0 was not necessarily issued from the same thread as the data request.Number of data vprefetch0 requests seen by the L1.Number of data vprefetch0 requests seen by the L1 which were dropped for any reason. A vprefetch0 can be dropped if the requested address matches another in-flight request or if it has a UC memtype.Number of data vprefetch0 requests seen by the L1 which missed L1. Does not include vprefetch1 requests which are counted in L1_DATA_PF1_DROP.Number of data vprefetch1 requests seen by the L1. This is not necessarily the same number as seen by the L2 because this count includes requests that are dropped by the core. A vprefetch1 can be dropped by the core if the requested address matches another in-flight request or if it has a UC memtype.Number of code read accesses that missed the L2 cache and were satisfied by another L2 cache. Can include promoted read misses that started as DATA accesses.Number of code read accesses that missed the L2 cache and were satisfied by main memory. Can include promoted read misses that started as DATA accesses.Number of data requests which hit an in-flight vprefetch1. The in-flight vprefetch1 was not necessarily issued from the same thread as the data request.Number of data vprefetch0 requests seen by the L2 which missed L2.Number of data vprefetch1 requests seen by the L2. Only counts vprefetch1 hits on A0 stepping.Number of data vprefetch1 requests seen by the L2 which were dropped for any reason.Number of data vprefetch1 requests seen by the L2 which missed L2. Does not include vprefetch2 requests which are counted in L2_DATA_PF2_DROP.Number of data read accesses that missed the L2 cache and were satisfied by another L2 cache. Can include promoted read misses that started as CODE accesses.Number of data read accesses that missed the L2 cache and were satisfied by main memory. Can include promoted read misses that started as CODE accesses.Number of data write (RFO) accesses that missed the L2 cache and were satisfied by another L2 cache.Number of data write (RFO) accesses that missed the L2 cache and were satisfied by main memory.L2 Read Hit E State, may include prefetches on A0 stepping.L2 Read Misses. Prefetch and demand requests to the same address will produce double counting.L2 received a victim request and responded with dataL2 Write HIT, may undercount on A0 stepping.Number of long code page walks, i.e. page walks that also missed the L2 uTLB. Subset of DATA_CODE_WALK eventNumber of long data page walks, i.e. page walks that also missed the L2 uTLB. Subset of DATA_PAGE_WALK eventNumber of data memory reads or writes that are paired in both pipes of the pipelineThe number of cycles microcode is executing. While microcode is executing, all other threads are stalled.Number of address generation interlock (AGI) stalls. An AGI occurring in both the U- and V- pipelines in the same clock signals this event twice.Number of pipeline flushes that occur. Pipeline flushes are caused by BTB misses on taken branches, mispredictions, exceptions, interrupts, and some segment descriptor loads.Number of address generation interlock (AGI) stalls due to vscatter* and vgather* instructions.Number of read transactions that were issued. In general each read transaction will read 1 64B cacheline. If there are alignment issues, then reads against multiple cache lines will each be counted individually.VPU L1 data cache readmiss. Counts the number of occurrences.Number of write transactions that were issued. . In general each write transaction will write 1 64B cacheline. If there are alignment issues, then write against multiple cache lines will each be counted individually.VPU L1 data cache write miss. Counts the number of occurrences.Counts the cumulative number of elements active (via mask) for VPU instructions issued.Counts the number of VPU instructions executed in both u- and v-pipes.VPU_INSTRUCTIONS_EXECUTED_V_PIPECounts the number of VPU instructions that paired and executed in the v-pipe.VPU stall on Register Dependency. Counts the number of occurrences. Dependencies will include RAW, WAW, WAR.Instruction length prediction delayDemand and L1 prefetcher requests rejected by L2Total cycles for all the page walks. (I-side and D-side)Total number of page walks. (I-side and D-side)Number of cycles when a D-side page walk is in progressNumber of cycles when a I-side page walk is in progressNumber of requests that were not accepted into the L2Q because the L2Q was FULLNumber of cycles the NIP stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache missesNumber of times the prediction (from the predecode cache) for instruction length is incorrectNumber of times the MSROM starts a flow of uopsNumber of cycles the divider is busyNumber of cycles when the allocation pipeline is stalled due to the RS for the MEC cluster is fullNumber of cycles when the allocation pipeline is stalled due any one of the RS being fullNumber of cycles when the front-end does not provide any instructions to be allocated for any reasonNumber of cycles when the front-end does not provide any instructions to be allocated but the back-end is not stalledNumber of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retireNumber of cycles when no uops are allocated and a RAT stall is assertedNumber of cycles when no uops are allocated and the ROB is full (less than 2 entries available)All mispredicted branches (Precise Event)Number of mispredicted conditional branch instructions retired (Precise Event)Number of mispredicted non-return branch instructions retired (Precise Event)Number of mispredicted return branch instructions retired (Precise Event)Number of mispredicted indirect call branch instructions retired (Precise Event)Number of mispredicted taken conditional branch instructions retired (Precise Event)Request: number of demand reads of partial cachelines (including UC, WC)Request: number of demand RFO requests to write to partial cache lines (includes UC, WT, WP)Request: number of UC instruction fetchesRequest: number of software prefetch requestsRequest: number of data cacheline reads generated by L1 prefetchersRequest: number of partial streaming store requestsRequest: counts one any other request that crosses IDI, including I/ORequest: combination of PF_IFETCH | DMND_IFETCH | UC_IFETCHPF_IFETCH:DMND_IFETCH:UC_IFETCHDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_L2_DATA_RD:PF_RFO:PF_IFETCH:PARTIAL_READ:PARTIAL_WRITE:UC_IFETCH:BUS_LOCKS:STRM_ST:SW_PREFETCH:PF_L1_DATA_RD:PARTIAL_STRM_ST:OTHERRequest: combination of DMND_DATA | PF_L1_DATA_RD | PF_L2_DATA_RDDMND_DATA_RD:PF_L1_DATA_RD:PF_L2_DATA_RDSupplier: counts L2 hits in M/E/S statesSnoop: counts number of times a snoop hits in the other module where no modified copies were found in the L1 cache of the other coreSnoop: counts number of times a snoop hits in the other module where modified copies were found in the L1 cache of the other coreSNP_NONE:SNP_MISS:SNP_HIT:SNP_HITM:NON_DRAMNumber of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise Event)Number of times forward was technically possible but did not occur because the store data was not available at the right timeNumber of retired stores that experienced cache line boundary splitsNumber of retired loads that experienced cache line boundary splits (Precise Event)Number of retired memory operations with lock semantics. These are either implicit locked instructions such as XCHG or instructions with an explicit LOCK prefixNumber of retired stores that are delayed because there is not a store address buffer availableNumber of load uops reissued from RehabQNumber of store uops reissued from RehabQNumber of load uops retired that miss in L1 data cache. Note that prefetch misses will not be countedNumber of load uops retired that hit L2 (Precise Event)Number of load uops retired that missed L2 (Precise Event)Number of load uops retired that had a DTLB miss (Precise Event)Number of load uops retired that had a UTLB missNumber of load uops retired that got data from the other core or from the other module and the line was modified (Precise Event)Number of reference cycles that the core is not in a halted state. The core enters the halted state when it is running the HLT instruction. In mobile systems, the core frequency may change from time to time. This event is not affected by core frequency changes but counts as if the core is running a the same maximum frequency all the timeNumber of baclears for return branchesNumber of baclears for conditional branchesAny retired branch instruction (Precise Event)Any Retired branch instruction (Precise Event)JCC instructions retired (Precise Event)Taken JCC instructions retired (Precise Event)Near call instructions retired (Precise Event)Near relative call instructions retired (Precise Event)Near indirect call instructions retired (Precise Event)Near ret instructions retired (Precise Event)Number of near indirect jmp and near indirect call instructions retired (Precise Event)Far branch instructions retired (Precise Event)Number of stalled cycles due to memory orderingNumber of stalled cycle due to FPU assistNumber of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims)Micro-ops retired that were supplied fro MSROMCount all instructions fetches from the instruction cacheCounts demand data reads that have any response type.Counts the number of load uops retired that hit the level 1 data cacheCounts the number of load uops retired.Counts cycles the floating point divider or integer divider or both are busy.  Does not imply a stall waiting for either divider.Counts the number of mispredicted branch instructions retired.Counts the number of branch instructions retired for all branch types.Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assist.Page walk completed due to an instruction fetch in a 4K page.Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.Counts requests to the Instruction Cache (ICache) for one or more bytes in a cache line and they do not hit in the ICache (miss).Page walk completed due to a demand data store to a 4K page.Counts memory requests originating from the core that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2.Page walk completed due to a demand load to a 4K page.Counts the number of unhalted core clock cycles. (Fixed event)Counts the number of unhalted reference clock cycles at TSC frequency.Counts the number of unhalted core clock cycles.Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)Page walk completed due to a demand load to a 2M or 4M page.Counts memory requests originating from the core that reference a cache line in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2.Page walk completed due to a demand data store to a 2M or 4M page.Counts requests to the Instruction Cache (ICache) for one or more bytes cache Line.Page walk completed due to an instruction fetch in a 2M or 4M page.Counts the number of store uops retired.Counts the number of load uops retired that miss in the level 2 cacheCounts the number of load uops retired that miss in the level 1 data cacheCounts the number of load uops retired that miss in the level 3 cacheCounts the number of load uops retired that hit in the level 2 cacheCounts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that have any response type.Instructions retired (any thread modifier supported in fixed counter)This is an alias for INSTRUCTION_RETIRED (any thread modifier supported in fixed counter)Counts the number of core cycles when divider is busy.Counts the number of core cycles when allocation pipeline is stalled.Counts the number of times that the machine clears.Number of times the MSROM starts a flow of uops.Counts the number of core cycles the fetch stalls.Counts the number of load micro-ops retired.Counts the number of MEC requests from the L2Q that reference a cache line were rejected.Number of requests not accepted into the L2Q because of any L2 queue reject condition.Counts the number of occurrences a retired load gets blocked.Counts the number of times the MSROM starts a flow of uops.Counts the number of core cycles when divider is busy.  Does not imply a stall waiting for the divider.Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry.Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full.Counts the number of core cycles when no micro-ops are allocated and the ROB is fullCounts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted.Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation.Counts the total number of core cycles when no micro-ops are allocated for any reason.Counts the number of mispredicted near CALL branch instructions retired.Counts the number of mispredicted near relative CALL branch instructions retired.Counts the number of mispredicted far branch instructions retired.Counts demand cacheable data and L1 prefetch data readsCounts Demand cacheable data writesCounts demand code reads and prefetch code readsCounts L2 data RFO prefetches (includes PREFETCHW instruction)Counts Partial reads (UC or WC and is valid only for Outstanding response type).Counts Partial writes (UC or WT or WP and should be programmed on PMC1)Counts UC code reads (valid only for Outstanding response type)Counts Bus locks and split lock requestsCounts Full streaming stores (WC and should be programmed on PMC1)Counts Partial streaming stores (WC and should be programmed on PMC1)Counts all streaming stores (WC and should be programmed on PMC1)PARTIAL_STREAMING_STORES:FULL_STREAMING_STORESCounts Demand cacheable data and L1 prefetch data read requestsDMND_DATA_RD:PARTIAL_READS:PF_SOFTWARE:PF_L1_DATA_RDCounts Demand cacheable data write requestsCounts Demand code reads and prefetch code read requestsDMND_DATA_RD:DMND_RFO:DMND_CODE_RD:PF_L2_RFO:PF_L2_CODE_RD:PARTIAL_READS:UC_CODE_READS:PF_SOFTWARE:PF_L1_DATA_RDAccounts for data responses from DRAM Local.Accounts for data responses from DRAM Far.Accounts for data responses from MCDRAM Local.Accounts for data responses from MCDRAM Far or Other tile L2 hit far.Accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.Accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.Accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.Accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.accounts for responses from any NON_DRAM system address. This includes MMIO transactionsaccounts for responses from MCDRAM (local and far)accounts for responses from DDR (local and far) accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateaccounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store (Precise Event).Counts the number of occurrences a retired load gets blocked because its address overlaps with a store whose data is not ready.Counts the number of occurrences a retired store that is a cache line split. Each split should be counted only once.Counts the number of occurrences a retired load that is a cache line split. Each split should be counted only once (Precise Event).Counts all the retired locked loads. It does not include stores because we would double count if we count stores.Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full.Counts any retired load that was pushed into the recycle queue for any reason.Counts any retired store that was pushed into the recycle queue for any reason.Counts the number of L2 cache missesCounts the total number of L2 cache references.Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted.Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included.Counts the total I-side page walks that are completed.Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included.Counts the total page walks completed (I-side and D-side)Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included.Counts the number of load micro-ops retired that miss in L1 D cache.Counts the number of load micro-ops retired that hit in the L2.Counts the number of load micro-ops retired that miss in the L2.Counts the number of load micro-ops retired that cause a DTLB miss.Counts the number of load micro-ops retired that caused micro TLB miss.Counts the loads retired that get the data from the other core in the same tile in M state.Counts all the load micro-ops retired.Counts all the store micro-ops retired.thread cycles when core is not haltedNumber of reference cycles that the cpu is not in a halted state. The core enters the halted state when it is running the HLT instruction. In mobile systems, the core frequency may change from time to time. This event is not affected by core frequency changes but counts as if the core is running a the same maximum frequency all the timeCounts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.Counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of core cycles the fetch stalled for all icache missesCounts the number of branch instructions retired (Precise Event)Counts the number of branch instructions retiredCounts the number of branch instructions retired that were conditional jumps.Counts the number of branch instructions retired that were conditional jumps and predicted taken.Counts the number of near CALL branch instructions retired.Counts the number of near relative CALL branch instructions retired.Counts the number of near indirect CALL branch instructions retired. (Precise Event)Counts the number of near RET branch instructions retired. (Precise Event)Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event)Counts the number of far branch instructions retired. (Precise Event)Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page.Counts the number of times the machine clears due to memory ordering hazardsCounts the number of floating operations retired that required microcode assistsCounts the number of MEC requests that were not accepted into the L2Q because of any L2  queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative pathCounts the number of MEC requests from the L2Q that reference a cache line excluding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times.Counts the number of micro-ops retired.Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS).Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.Counts all instruction fetches that hit the instruction cache.Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.Counts all instruction fetches, including uncacheable fetches.Intel AlderLake Gracemont (E-Core)Intel AlderLake GoldenCove (P-Core)Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branchesCounts the total number of branch instructions retired for all branch typesCounts the total number of mispredicted branch instructions retired for all branch typesCounts the number of unhalted core clock cyclesCounts the number of page walks completed due to load DTLB misses to any page sizeCounts the number of page walks completed due to store DTLB misses to any page sizeCounts the number of instruction cache missesCounts the total number of instructions retired. (Fixed event)Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBsThis event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not readyCounts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 missCounts the number of cacheable memory requests that miss in the LLC. Counts on a per core basisCounts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code pageCounts the number of cycles the core is stalled due to a demand load which hit in the L2 cacheCounts the number of load uops retired that hit in the L2 cacheCounts the number of cycles that uops are blocked due to a store buffer full conditionCounts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabledCounts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY]Counts demand data reads that have any type of responseCounts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retiresCounts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clearCounts the total number of issue slots every cycle that were not consumed by the backend due to backend stallsCounts the total number of issue slots every cycle that were not consumed by the backend due to frontend stallsCounts the total number of consumed retirement slotsCounts the total number of uops retiredCounts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt)Counts the number of integer divide uops retiredCounts the number of uops that are from complex flows issued by the micro-sequencer (MS)Counts the number of x87 uops retired, includes those in MS flowsCounts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARSCounts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARSCounts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS)Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stallsCounts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitationsCounts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache missesCounts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache missesCounts the number of issue slots every cycle that were not delivered by the frontend due to ITLB missesCounts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorizedCounts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodesCounts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictionsCounts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uopsCounts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uopsCounts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls)Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clearsCounts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguationCounts the number of issue slots every cycle that were not consumed by the backend due to branch mispredictsCounts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke)Counts modified writebacks from L1 cache and L2 cache that have any type of responseCounts demand data reads that were supplied by the L3 cacheCounts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedCounts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwardedCounts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwardedCounts demand data reads that were not supplied by the L3 cacheCounts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of responseCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cacheCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cacheCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]Counts streaming stores that have any type of responseCounts the number of load uops retiredCounts the number of store uops retiredCounts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabledCounts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabledCounts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabledCounts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabledCounts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabledCounts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabledCounts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabledCounts the number of retired split load uopsCounts the number of stores uops retired. Counts with or without PEBS enabledload buffer, store buffer or RSV fullCounts the number of cycles that uops are blocked due to a load buffer full conditionCounts the number of cycles that uops are blocked due to an RSV full conditionCounts the number of load uops retired that hit in DRAMCounts the number of load uops retired that hit in the L3 cacheCounts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM)Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM)Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cacheCounts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/MCounts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM)Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM)Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/MCounts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPUCounts the number of floating point operations retired that required microcode assistCounts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguationCounts the number of machines clears due to memory renamingCounts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occursCounts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAPCounts the number of cacheable memory requests that access the LLC. Counts on a per core basisCounts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retiresCounts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB missCounts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiringCounts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block casesCounts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalkCounts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address matchThis event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIASCounts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias checkCounts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cacheCounts the number of page walks completed due to instruction fetch misses to any page sizeCounts the total number of instructions retiredCounts the number of requests to the instruction cache for one or more bytes of a cache lineCounts the number of unhalted reference clock cycles at TSC frequencyCounts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retiredCounts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retiredCounts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retiredCounts the number of mispredicted near indirect CALL branch instructions retiredThis event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALLThis event is deprecated. Refer to new event BR_MISP_RETIRED.CONDCounts the number of mispredicted near taken branch instructions retiredThis event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECTCounts the number of mispredicted near RET branch instructions retiredThis event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKENThis event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALLCounts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branchesCounts the number of taken JCC (Jump on Conditional Code) branch instructions retiredCounts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and returnCounts the number of near indirect JMP and near indirect CALL branch instructions retiredCounts the number of near indirect CALL branch instructions retiredThis event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALLThis event is deprecated. Refer to new event BR_INST_RETIRED.CONDCounts the number of near CALL branch instructions retiredCounts the number of near RET branch instructions retiredCounts the number of near taken branch instructions retiredThis event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECTCounts the number of near relative CALL branch instructions retiredThis event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURNThis event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKENThis event is deprecated. Refer to new event ARITH.FPDIV_ACTIVECounts all microcode FP assistsClears due to Unknown BranchesAll branch instructions retiredAll mispredicted branch instructions retiredCycles while L2 cache miss demand load is outstandingStalls caused by changing prefix length of the instructionDSB-to-MITE switch true penalty cyclesPage walks completed due to a demand data load to a 4K pagePage walks completed due to a demand data store to a 4K pageCycles total of 1 uop is executed on all ports and Reservation Station was not emptyCounts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructionsRetired Instructions who experienced a critical DSB missUops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]integer ADD, SUB, SAD 128-bit vector instructionsCounts the number of cache lines replaced in L1 data cacheCounts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetchCycles Uops delivered by the LSD, but didn't come from the decoderCycles while L1 cache miss demand load is outstandingRetired load instructions that miss the STLBCompleted demand load uops that miss the L1 d-cacheRetired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cacheRetired instructions with at least 1 uncacheable load or lockCounts randomly selected loads when the latency from first dispatch to completion is greater latency threshold in ldlat=Increments whenever there is an update to the LBR arrayCycles where at least 1 outstanding demand data read request is pendingCounts cycles where the pipeline is stalled due to serializing operationsCounts bus locks, accounts for cache line split locks and UC locksNumber of PREFETCHNTA instructions executedTopdown events using PERF_METRICS supportRetired uops except the last uop of each instructionCycles without actually retired uopsThis event is deprecated. Refer to new event UOPS_RETIRED.STALLSCycles at least 1 micro-op is executed from any thread on physical coreCycles at least 2 micro-op is executed from any thread on physical coreCycles at least 3 micro-op is executed from any thread on physical coreCycles at least 4 micro-op is executed from any thread on physical coreCounts number of cycles no uops were dispatched to be executed on this threadThis event is deprecated. Refer to new event UOPS_EXECUTED.STALLSCounts the number of uops to be executed per-thread each cycleCounts the number of x87 uops dispatchedTMA slots where no uops were being issued due to lack of back-end resources (Topdown L1)TMA slots wasted due to incorrect speculations (Topdown L1)TMA slots wasted due to memory accesses (TopdownL2)TMA slots where instructions are retiring (Topdown L1)Number of PREFETCHW instructions executedNumber of PREFETCHT0 instructions executedNumber of PREFETCHT1 or PREFETCHT2 instructions executedCounts end of periods where the Reservation Station (RS) was emptyCycles stalled due to no store buffers available. (not including draining form sync)This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RDFor every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1For every cycle, increments by the number of outstanding demand data read requests pendingFor every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cacheCounts demand data read requests that miss the L3 cacheCounts demand data reads that were supplied by DRAMCounts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modifiedCounts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting coreCounts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of responseCounts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modifiedCounts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cacheCounts randomly selected loads when the latency from first dispatch to completion is greater than 128 cyclesCounts randomly selected loads when the latency from first dispatch to completion is greater than 16 cyclesCounts randomly selected loads when the latency from first dispatch to completion is greater than 256 cyclesCounts randomly selected loads when the latency from first dispatch to completion is greater than 32 cyclesCounts randomly selected loads when the latency from first dispatch to completion is greater than 4 cyclesCounts randomly selected loads when the latency from first dispatch to completion is greater than 512 cyclesCounts randomly selected loads when the latency from first dispatch to completion is greater than 64 cyclesCounts randomly selected loads when the latency from first dispatch to completion is greater than 8 cyclesRetired memory store access operations. A PDist event for PEBS Store Latency FacilityNumber of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1Retired load instructions with locked accessRetired load instructions that split across a cacheline boundaryRetired store instructions that split across a cacheline boundaryRetired store instructions that miss the STLBExecution stalls while L1 cache miss demand load is outstandingNumber of machine clears due to memory ordering conflictsSelf-modifying code (SMC) detectedCycles optimal number of Uops delivered by the LSD, but did not come from the decoderNumber of Uops delivered by the LSDThe number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useLoads blocked due to overlapping with a preceding store that cannot be forwardedRead requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS]SW prefetch requests that hit L2 cacheSW prefetch requests that miss L2 cacheNumber of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailabilityNumber of phases a demand request has waited due to L1D Fill Buffer (FB) unavailabilityThis event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLSNumber of cycles a demand request has waited due to L1D due to lack of L2 resourcesCycles with L1D load Misses outstandingInstruction fetch requests that miss the ITLB and hit the STLBCycles when at least one PMH is busy with a page walk for code (instruction fetch) requestNumber of page walks outstanding for an outstanding code request in the PMH each cycleinteger ADD, SUB, SAD 256-bit vector instructionsCounts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered pathBubble cycles of BAClear (Unknown Branch)Iterations of Repeat string retired instructionsRetired Instructions who experienced DSB missRetired Instructions who experienced iTLB true missRetired Instructions who experienced Instruction L1 Cache true missRetired Instructions who experienced Instruction L2 Cache true missRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stallRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stallRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stallRetired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stallRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stallRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stallRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stallRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stallRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stallRetired Instructions who experienced STLB (2nd level TLB) true missCounts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementCounts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCycles total of 2 uops are executed on all ports and Reservation Station was not emptyCycles total of 3 uops are executed on all ports and Reservation Station was not emptyCycles total of 4 uops are executed on all ports and Reservation Station was not emptyExecution stalls while memory subsystem has an outstanding loadCycles where the Store Buffer was full and no loads caused an execution stallCycles no uop executed while RS was not empty, the SB was not full and there was no outstanding loadStores that miss the DTLB and hit the STLBCycles when at least one PMH is busy with a page walk for a storePage walks completed due to a demand data store to a 1G pagePage walks completed due to a demand data store to a 2M/4M pageNumber of page walks outstanding for a store in the PMH each cycleLoads that miss the DTLB and hit the STLBCycles when at least one PMH is busy with a page walk for a demand loadPage walks completed due to a demand data load to a 1G pagePage walks completed due to a demand data load to a 2M/4M pageNumber of page walks outstanding for a demand load in the PMH each cycleCycles the Microcode Sequencer is busyCycles while memory subsystem has an outstanding loadExecution stalls while L2 cache miss demand load is outstandingExecution stalls while L3 cache miss demand load is outstandingCore clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized stateCore clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized stateCore clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI stateCycle counts are evenly distributed between active threads in the CoreCore crystal clock cycles when this thread is unhalted and the other thread is haltedCore crystal clock cycles. Cycle counts are evenly distributed between active threads in the CoreReference cycles when the core is not in halt stateMispredicted conditional branch instructions retiredMispredicted non-taken conditional branch instructions retirednumber of branch instructions retired that were mispredicted and takenMispredicted indirect CALL retiredConditional branch instructions retiredNot taken branch instructions retiredTaken conditional branch instructions retiredFar branch instructions retiredDirect and indirect near call instructions retiredTaken branch instructions retiredNumber of occurrences where a microcode assist is invoked by hardwareThis event is deprecated. Refer to new event ARITH.DIV_ACTIVECycles when divide unit is busy executing divide or square root operationsThis event counts the cycles the integer divider is busyThis event is deprecated. Refer to new event ARITH.IDIV_ACTIVEIntel Knights Mill IMC UCLK 1 uncoreIntel KnightLanding IMC UCLK 1 uncoreIntel Knights Mill IMC UCLK 0 uncoreIntel KnightLanding IMC UCLK 0 uncoreIntel Knights Mill IMC 5 uncoreIntel KnightLanding IMC 5 uncoreIntel Knights Mill IMC 4 uncoreIntel KnightLanding IMC 4 uncoreIntel Knights Mill IMC 3 uncoreIntel KnightLanding IMC 3 uncoreIntel Knights Mill IMC 2 uncoreIntel KnightLanding IMC 2 uncoreIntel Knights Mill IMC 1 uncoreIntel KnightLanding IMC 1 uncoreIntel Knights Mill IMC 0 uncoreIntel KnightLanding IMC 0 uncoreIntel Knights Mill EDC_ECLK_7 uncoreIntel KnightLanding EDC_ECLK_7 uncoreIntel Knights Mill EDC_ECLK_6 uncoreIntel KnightLanding EDC_ECLK_6 uncoreIntel Knights Mill EDC_ECLK_5 uncoreIntel KnightLanding EDC_ECLK_5 uncoreIntel Knights Mill EDC_ECLK_4 uncoreIntel KnightLanding EDC_ECLK_4 uncoreIntel Knights Mill EDC_ECLK_3 uncoreIntel KnightLanding EDC_ECLK_3 uncoreIntel Knights Mill EDC_ECLK_2 uncoreIntel KnightLanding EDC_ECLK_2 uncoreIntel Knights Mill EDC_ECLK_1 uncoreIntel KnightLanding EDC_ECLK_1 uncoreIntel Knights Mill EDC_ECLK_0 uncoreIntel KnightLanding EDC_ECLK_0 uncoreIntel Knights Mill EDC_UCLK_7 uncoreIntel KnightLanding EDC_UCLK_7 uncoreIntel Knights Mill EDC_UCLK_6 uncoreIntel KnightLanding EDC_UCLK_6 uncoreIntel Knights Mill EDC_UCLK_5 uncoreIntel KnightLanding EDC_UCLK_5 uncoreIntel Knights Mill EDC_UCLK_4 uncoreIntel KnightLanding EDC_UCLK_4 uncoreIntel Knights Mill EDC_UCLK_3 uncoreIntel KnightLanding EDC_UCLK_3 uncoreIntel Knights Mill EDC_UCLK_2 uncoreIntel KnightLanding EDC_UCLK_2 uncoreIntel Knights Mill EDC_UCLK_1 uncoreIntel KnightLanding EDC_UCLK_1 uncoreIntel Knights Mill EDC_UCLK_0 uncoreIntel KnightLanding EDC_UCLK_0 uncoreEDC ECLK clockticks (generic counters)Counts total number of EDC RPQ insersCounts total number of EDC WPQ insersEDC UCLK clockticks (generic counters)Number of EDC Access Hits or Misses.Intel Knights Mill CHA 37 uncoreIntel KnightLanding CHA 37 uncoreIntel Knights Mill CHA 36 uncoreIntel KnightLanding CHA 36 uncoreIntel Knights Mill CHA 35 uncoreIntel KnightLanding CHA 35 uncoreIntel Knights Mill CHA 34 uncoreIntel KnightLanding CHA 34 uncoreIntel Knights Mill CHA 33 uncoreIntel KnightLanding CHA 33 uncoreIntel Knights Mill CHA 32 uncoreIntel KnightLanding CHA 32 uncoreIntel Knights Mill CHA 31 uncoreIntel KnightLanding CHA 31 uncoreIntel Knights Mill CHA 30 uncoreIntel KnightLanding CHA 30 uncoreIntel Knights Mill CHA 29 uncoreIntel KnightLanding CHA 29 uncoreIntel Knights Mill CHA 28 uncoreIntel KnightLanding CHA 28 uncoreIntel Knights Mill CHA 27 uncoreIntel KnightLanding CHA 27 uncoreIntel Knights Mill CHA 26 uncoreIntel KnightLanding CHA 26 uncoreIntel Knights Mill CHA 25 uncoreIntel KnightLanding CHA 25 uncoreIntel Knights Mill CHA 24 uncoreIntel KnightLanding CHA 24 uncoreIntel Knights Mill CHA 23 uncoreIntel KnightLanding CHA 23 uncoreIntel Knights Mill CHA 22 uncoreIntel KnightLanding CHA 22 uncoreIntel Knights Mill CHA 21 uncoreIntel KnightLanding CHA 21 uncoreIntel Knights Mill CHA 20 uncoreIntel KnightLanding CHA 20 uncoreIntel Knights Mill CHA 19 uncoreIntel KnightLanding CHA 19 uncoreIntel Knights Mill CHA 18 uncoreIntel KnightLanding CHA 18 uncoreIntel Knights Mill CHA 17 uncoreIntel KnightLanding CHA 17 uncoreIntel Knights Mill CHA 16 uncoreIntel KnightLanding CHA 16 uncoreIntel Knights Mill CHA 15 uncoreIntel KnightLanding CHA 15 uncoreIntel Knights Mill CHA 14 uncoreIntel KnightLanding CHA 14 uncoreIntel Knights Mill CHA 13 uncoreIntel KnightLanding CHA 13 uncoreIntel Knights Mill CHA 12 uncoreIntel KnightLanding CHA 12 uncoreIntel Knights Mill CHA 11 uncoreIntel KnightLanding CHA 11 uncoreIntel Knights Mill CHA 10 uncoreIntel KnightLanding CHA 10 uncoreIntel Knights Mill CHA 9 uncoreIntel KnightLanding CHA 9 uncoreIntel Knights Mill CHA 8 uncoreIntel KnightLanding CHA 8 uncoreIntel Knights Mill CHA 7 uncoreIntel KnightLanding CHA 7 uncoreIntel Knights Mill CHA 6 uncoreIntel KnightLanding CHA 6 uncoreIntel Knights Mill CHA 5 uncoreIntel KnightLanding CHA 5 uncoreIntel Knights Mill CHA 4 uncoreIntel KnightLanding CHA 4 uncoreIntel Knights Mill CHA 3 uncoreIntel KnightLanding CHA 3 uncoreIntel Knights Mill CHA 2 uncoreIntel KnightLanding CHA 2 uncoreIntel Knights Mill CHA 1 uncoreIntel KnightLanding CHA 1 uncoreIntel Knights Mill CHA 0 uncoreIntel KnightLanding CHA 0 uncoreIngress Occupancy. Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycleIngress Allocations. Counts number of allocations per cycle into the specified Ingress queueUNC_H_INGRESS_RETRY_IRQ0_REJECTUNC_H_INGRESS_RETRY_IRQ01_REJECTUNC_H_INGRESS_RETRY_PRQ0_REJECTUNC_H_INGRESS_RETRY_PRQ1_REJECTUNC_H_INGRESS_RETRY_IPQ0_REJECTUNC_H_INGRESS_RETRY_IPQ1_REJECTUNC_H_INGRESS_RETRY_ISMQ0_REJECTUNC_H_INGRESS_RETRY_REQ_Q0_RETRYREQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)UNC_H_INGRESS_RETRY_REQ_Q1_RETRYUNC_H_INGRESS_RETRY_ISMQ0_RETRYUNC_H_INGRESS_RETRY_OTHER0_RETRYUNC_H_INGRESS_RETRY_OTHER1_RETRYCache Lookups. Counts the number of times the LLC was accessed.Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subeventMiscellaneous events in the ChaCMS Agent0 AD Credits Acquired.CMS Agent0 AD Credits Occupancy.UNC_H_AG0_AD_CRD_OCCUPANCY_EXTCMS Agent0 AD Credits Acquired For Transgress.CMS Agent1 AD Credits Acquired .CMS Agent1 AD Credits Occupancy.UNC_H_AG1_AD_CRD_OCCUPANCY_EXTCMS Agent0 BL Credits Acquired.CMS Agent0 BL Credits Occupancy.UNC_H_AG0_BL_CRD_OCCUPANCY_EXTCMS Agent1 BL Credits Acquired.CMS Agent1 BL Credits Occupancy.UNC_H_AG1_BL_CRD_OCCUPANCY_EXTUNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_ADStall on No AD Transgress Credits.UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXTUNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_ADUNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXTUNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BLUNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXTUNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BLUNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXTCycles CMS Vertical Egress Queue Is Full.Cycles CMS Vertical Egress Queue Is Not Empty.CMS Vertical Egress Injection Starvation.CMS Horizontal Egress Occupancy.CMS Horizontal Egress Inserts.Cycles CMS Horizontal Egress Queue is Full.Cycles CMS Horizontal Egress Queue is Not Empty.CMS Horizontal Egress Injection Starvation.Number of incoming messages from the Vertical ring that were bounced, by ring type.Number of incoming messages from the Horizontal ring that were bounced, by ring type.Vertical ring sink starvation count.Horizontal ring sink starvation count.Counts cycles in throttle mode.Counts cycles source throttling is assertedCounts the number of cycles that the Vertical AD ring is being used at this ring stop.Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.Counts the number of cycles that the Vertical AK ring is being used at this ring stop.Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.Counts the number of cycles that the Vertical BL ring is being used at this ring stop.Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.Counts the number of cycles that the Vertical IV ring is being used at this ring stop.Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements.Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh.Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh.Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress.Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority.Counts the number of times that an RFO hits in S state.Any reject from request queue0Victimized Lines matching the NID filter.Victimized Lines does not matching the NID.Intel Knights Mill M2PCIe uncoreIntel Knights Landing M2PCIe uncoreIngress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not emptyEgress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not emptyEgress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queueEgress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is fullReferences per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitectureRetired mispredicted branch instructions (Precise Event)Decode restrictions due to predicting wrong instruction lengthLoad uops that split a page (Precise Event)Unfilled issue slots per cycle because of a full resource in the backendLoad uops retired that hit L1 data cache (Precise Event)L1 Cache evictions for dirty dataCycles where code-fetch is stalled and an ICache miss is outstanding.  This is not the same as an ICache MissUops requested but not-delivered to the back-end per cycleNumber of mispredicted branch instructions retiredLoad uops retired (Precise Event)Uops issued to the back end per cycleUnhalted reference cycles. Ticks at constant reference frequencyNumber of branch instructions retiredDuration of D-side page-walks in cyclesBACLEARs asserted for any branch typeCore cycles when core is not halted  (Fixed event)Core clock cycles whenever the clock signal on the specific core is running (not halted)Reference cycles when core is not halted  (Fixed event)Reference cycles when core is not haltedBACLEARs asserted for return branchBACLEARs asserted for conditional branchDuration of I-side pagewalks in cyclesDuration of page-walks in cyclesStore uops retired (Precise Event)Load uops retired that missed the DTLB (Precise Event)Store uops retired that missed the DTLB (Precise Event)Memory uops retired that missed the DTLB (Precise Event)Locked load uops retired (Precise Event)Load uops retired that split a cache-line (Precise Event)Stores uops retired that split a cache-line (Precise Event)Memory uops retired that split a cache-line (Precise Event)Retired conditional branch instructions that were taken (Precise Event)Retired near relative call instructions (Precise Event)Retired near indirect call instructions (Precise Event)Retired near return instructions (Precise Event)Retired instructions of near indirect Jmp or call (Precise Event)Retired far branch instructions (Precise Event)Machine cleas due to memory ordering issueMachine clears due to FP assistsMachine clears due to memory disambiguationRequest: number of data cacheline reads generated by L2 prefetcherRequest: number of partil readsRequest: number of partial writesRequest: number of uncached code readsRequest: number of streaming store requests for full cachelineRequest: number of cacheline requests due to software prefetchRequest: number of data cacheline reads generated by L1 data prefetcherRequest: number of streaming store requests for partial cachelineRequest: number of streaming store requests for partial or full cachelineRequest: number of prefetch data readsPF_DATA_RD:SW_PF:PF_L1_DATA_RDL2_MISS_SNP_MISS_OR_NO_SNOOP_NEEDEDSnoop: counts number true misses to this processor module for which a snoop request missed the other processor module or no snoop was neededSnoop: counts number of times a snoop request hits the other processor module but no data forwarding is neededSnoop: counts number of times a snoop request hits in the other processor module or other core's L1 where a modified copy (M-state) is foundL2_MISS_SNP_MISS_OR_NO_SNOOP_NEEDED:L2_MISS_HIT_OTHER_CORE_NO_FWD:L2_MISS_HITM_OTHER_CORE:L2_MISS_SNP_NON_DRAMOutstanding request:  counts weighted cycles of outstanding offcore requests of the request type specified in the bits 15:0 of offcore_response from the time the XQ receives the request and any response received. Bits 37:16 must be set to 0. This is only available for offcore_response_0MS uops retired (Precise Event)Cycles the integer divide unit is busyCycles the FP divide unit is busyLoads blocked because address in not in the UTLB (Precise Event)Loads blocked due to store forward restriction (Precise Event)Loads blocked due to store data not ready (Precise Event)Loads blocked because address has 4k partial address false dependence (Precise Event)Load uops retired that missed L1 data cache (Precise Event)Load uops retired that hit L2 (Precise Event)Load uops retired that missed L2 (Precise Event)Memory uop retired where cross core or cross module HITM occurred (Precise Event)Loads retired that hit WCB (Precise Event)Loads retired that came from DRAM (Precise Event)Unfilled issue slots per cycle to recoverUnfilled issue slots per cycleCounts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.  Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.Store uops that split a page (Precise Event)Retired mispredicted conditional branch instructions (Precise Event)Retired mispredicted conditional branch instructions that were taken (Precise Event)Retired mispredicted near indirect call instructions (Precise Event)Retired mispredicted near return instructions (Precise Event)Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise Event)Cycles pending interrupts are maskedReferences per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitectureReferences per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecturepmu: %s event%d:%s umask%d: %s :: invalid bit field
pmu: %s event%d:%s :: more than one default umask
pmu: %s event%d:%s :: no event mask end-marker
[0x%lx 0x%lx 0x%lx usr=%d os=%d tag_ena=%d tag_val=%d evmask=0x%x evsel=0x%x escr_sel=0x%x comp=%d cmpl=%d thr=%d e=%devent threshold in range [0-15]The duration (in clock cycles) of the operating modes of the trace cache and decode engine in the processor packageBoth logical CPUs in deliver modeLogical CPU 0 in deliver mode and logical CPU 1 in build modeLogical CPU 0 in deliver mode and logical CPU 1 either halted, under machine clear condition, or transitioning to a long microcode flowLogical CPU 0 in build mode and logical CPU 1 is in deliver modeBoth logical CPUs in build modeLogical CPU 0 in build mode and logical CPU 1 either halted, under machine clear condition, or transitioning to a long microcode flowLogical CPU 0 either halted, under machine clear condition, or transitioning to a long microcode flow, and logical CPU 1 in deliver modeLogical CPU 0 either halted, under machine clear condition, or transitioning to a long microcode flow, and logical CPU 1 in build modeInstruction fetch requests by the Branch Prediction UnitTranslations using the Instruction Translation Look-Aside BufferCanceling of various types of requests in the Data cache Address Control unit (DAC)Replayed because no store request buffer is availableCompletions of a load split, store split, uncacheable (UC) split, or UC loadLoad split completed, excluding UC/WC loadsReplayed events at the load portReplayed events at the store portCount of times the memory order buffer (MOB) caused a load operation to be replayedReplayed because of unknown store addressReplayed because of unknown store dataReplayed because of partially overlapped data access between the load and store operationsReplayed because the lower 4 bits of the linear address do not match between the load and store operationsPage walks that the page miss handler (PMH) performsPage walk for a data TLB miss (load or store)Page walk for an instruction TLB missCache references (2nd or 3rd level caches) as seen by the bus unit. Read types include both load and RFO, and write types include writebacks and evictionsRead 2nd level cache hit SharedRead 2nd level cache hit ExclusiveRead 2nd level cache hit ModifiedRead 3rd level cache hit SharedRead 3rd level cache hit ExclusiveRead 3rd level cache hit ModifiedA writeback lookup from DAC misses the 2nd level cache (unlikely to happen)Count of various types of transactions on the bus. A count is generated each time a transaction is allocated into the IOQ that matches the specified mask bits. An allocated entry can be a sector (64 bytes) or a chunk of 8 bytes. Requests are counted once per retry. All 'TYPE_BIT*' event-masks together are treated as a single 5-bit valueCount UC memory access entriesCount WC memory access entriesCount write-through (WT) memory access entriesCount write-protected (WP) memory access entriesCount WB memory access entriesCount all store requests driven by processor, as opposed to other processor or DMACount all requests driven by other processors or DMAInclude HW and SW prefetch requests in the countNumber of entries (clipped at 15) in the IOQ that are active. An allocated entry can be a sector (64 bytes) or a chunk of 8 bytes. This event must be programmed in conjunction with IOQ_allocation. All 'TYPE_BIT*' event-masks together are treated as a single 5-bit valueCount of DRDY or DBSY events that occur on the front side busCount when this processor drives data onto the bus. Includes writes and implicit writebacksCount when this processor reads data from the bus. Includes loads and some PIC transactions. Count DRDY events that we drive. Count DRDY events sampled that we ownCount when data is on the bus but not being sampled by the processor. It may or may not be driven by this processorCount when this processor reserves the bus for use in the next bus cycle in order to drive dataCount when some agent reserves the bus for use in the next bus cycle to drive data that this processor will sampleCount when some agent reserves the bus for use in the next bus cycle to drive data that this processor will NOT sample. It may or may not be being driven by this processorAllocations in the Bus Sequence Unit (BSQ). The event mask bits consist of four sub-groups: request type, request length, memory type, and a sub-group consisting mostly of independent bits (5 through 10). Must specify a mask for each sub-groupAlong with REQ_TYPE1, request type encodings are: 0 - Read (excludes read invalidate), 1 - Read invalidate, 2 - Write (other than writebacks), 3 - Writeback (evicted from cache)Along with REQ_TYPE0, request type encodings are: 0 - Read (excludes read invalidate), 1 - Read invalidate, 2 - Write (other than writebacks), 3 - Writeback (evicted from cache)Along with REQ_LEN1, request length encodings are: 0 - zero chunks, 1 - one chunk, 3 - eight chunksAlong with REQ_LEN0, request length encodings are: 0 - zero chunks, 1 - one chunk, 3 - eight chunksRequest type is input or outputRequest type is a bus 8-byte chunk split across an 8-byte boundary0: Request type is HW.SW prefetch. 1: Request type is a demandAlong with MEM_TYPE1 and MEM_TYPE2, memory type encodings are: 0 - UC, 1 - USWC, 4- WT, 5 - WP, 6 - WBAlong with MEM_TYPE0 and MEM_TYPE2, memory type encodings are: 0 - UC, 1 - USWC, 4- WT, 5 - WP, 6 - WBAlong with MEM_TYPE0 and MEM_TYPE1, memory type encodings are: 0 - UC, 1 - USWC, 4- WT, 5 - WP, 6 - WBNumber of BSQ entries (clipped at 15) currently active (valid) which meet the subevent mask criteria during allocation in the BSQ. Active request entries are allocated on the BSQ until de-allocated. De-allocation of an entry does not necessarily imply the request is filled. This event must be programmed in conjunction with BSQ_allocationNumber of times an assist is requested to handle problems with input operands for SSE/SSE2/SSE3 operations; most notably denormal source operands when the DAZ bit isn't setCount assists for SSE/SSE2/SSE3 uopsNumber of packed single-precision uopsCount all uops operating on packed single-precisions operandsTag this event with tag bit 0 for retirement counting with execution_eventTag this event with tag bit 1 for retirement counting with execution_eventTag this event with tag bit 2 for retirement counting with execution_eventTag this event with tag bit 3 for retirement counting with execution_eventNumber of packed double-precision uopsCount all uops operating on packed double-precisions operandsNumber of scalar single-precision uopsCount all uops operating on scalar single-precisions operandsNumber of scalar double-precision uopsCount all uops operating on scalar double-precisions operandsNumber of MMX instructions which operate on 64-bit SIMD operandsCount all uops operating on 64-bit SIMD integer operands in memory or MMX registersNumber of MMX instructions which operate on 128-bit SIMD operandsCount all uops operating on 128-bit SIMD integer operands in memory or MMX registersNumber of x87 floating-point uopsMiscellaneous events detected by the TC. The counter will count twice for each occurrenceCounts the time during which a processor is not stoppedThe processor is active (includes the handling of HLT STPCLK and throttlingNumber of times that uop delivery changed from TC to MS ROMNumber of valid uops written to the uop queueThe uops being written are from TC build modeThe uops being written are from TC deliver modeThe uops being written are from microcode ROMNumber of retiring mispredicted branches by typeReturns, indirect calls, or indirect jumpsNumber of retiring branches by typeOccurrences of latency or stalls in the AllocatorA stall due to lack of store buffersNumber of Write Combining Buffer operationsWC Buffer evictions of all causesWC Buffer eviction; no WC buffer is availableNumber of back-to-back bus cyclesNumber of bus-not-ready conditionsNumber of snoop hit modified bus trafficCount of different types of responsesNumber of retirements of tagged uops which are specified through the front-end tagging mechanismNumber of retirements of tagged uops which are specified through the execution tagging mechanism. The event-mask allows from one to four types of uops to be taggedNumber of retirements of tagged uops which are specified through the replay tagging mechanismVirtual mask for L1 cache load miss replaysVirtual mask for L2 cache load miss replaysVirtual mask for DTLB load miss replaysVirtual mask for DTLB store miss replaysVirtual mask for all DTLB miss replaysVirtual mask for tagged mispredicted branch replaysVirtual mask for MOB load replaysVirtual mask for split load replays. Use with load_port_replay eventVirtual mask for split store replays. Use with store_port_replay eventNumber of instructions retired during a clock cycleNon-bogus instructions that are not taggedNon-bogus instructions that are taggedBogus instructions that are not taggedBogus instructions that are taggedNumber of uops retired during a clock cycleThis event is used in conjunction with with the front-end mechanism to tag load and store uopsNumber of retirements of a branchNumber of retirements of mispredicted IA-32 branch instructionsThe retired instruction is not bogusNumber of retirements of x87 instructions that required special handlingNumber of occurrences when the entire pipeline of the machine is clearedCounts for a portion of the many cycles while the machine is cleared for any cause. Use edge-triggering for this bit only to get a count of occurrences versus a durationIncrements each time the machine is cleared due to memory ordering issuesIncrements each time the machine is cleared due to self-modifying code issuesInstructions that have completed and retired during a clock cycle (models 3, 4, 6 only)DATA_CACHE_REFILLS_FROM_SYSTEMData Cache Refills from SystemRetired Instructions (includes exceptions, interrupts, resyncs)RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRetired Branch Resyncs (only non-control transfer branches)INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingInvalid, Shared, Exclusive, Owned, ModifiedShared, Exclusive, Owned, Modified State RefillsCycles with no FPU Ops RetiredDispatched Fast Flag FPU OperationsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline restart due to self-modifying codePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline restart due to probe hitData Cache Refills from L2 or SystemMICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESSMicroarchitectural Late Cancel of an AccessMICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESSMicroarchitectural Early Cancel of an AccessSCRUBBER_SINGLE_BIT_ECC_ERRORSSingle-bit ECC Errors Recorded by ScrubberPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsSystem Read Responses by Coherency StateINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemPIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEPipeline Restart Due to Instruction Stream ProbeRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_MMX_AND_FP_INSTRUCTIONSRETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSRetired Fastpath Double Op InstructionsDISPATCH_STALL_FOR_BRANCH_ABORTDispatch Stall for Branch Abort to RetireDISPATCH_STALL_FOR_SERIALIZATIONDispatch Stall for SerializationDISPATCH_STALL_FOR_SEGMENT_LOADDispatch Stall for Segment LoadDISPATCH_STALL_FOR_REORDER_BUFFER_FULLDispatch Stall for Reorder Buffer FullDISPATCH_STALL_FOR_RESERVATION_STATION_FULLDispatch Stall for Reservation Station FullDISPATCH_STALL_WAITING_FOR_ALL_QUIETDispatch Stall Waiting for All QuietDISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNCDispatch Stall for Far Transfer or Resync to RetireMEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWSMemory Controller Page Table OverflowsMemory Controller Bypass Counter SaturationProbe Responses and Upstream RequestsHyperTransport Link 0 Transmit BandwidthHyperTransport Link 1 Transmit BandwidthHyperTransport Link 2 Transmit BandwidthGART aperture hit on access from CPUGART aperture hit on access from I/OProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)Probe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_DISPLAY_REFRESH_READSUpstream display refresh readsUPSTREAM_NON_DISPLAY_REFRESH_READSUpstream non-display refresh readsNonPosted SzWr Byte (1-32 bytes) Legacy or mapped I/O, typically 1-4 bytesNonPosted SzWr Dword (1-16 dwords) Legacy or mapped I/O, typically 1 dwordPosted SzWr Byte (1-32 bytes) Sub-cache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPosted SzWr Dword (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesSzRd Byte (4 bytes) Legacy or mapped I/OSzRd Dword (1-16 dwords) Block-oriented DMA reads, typically cache-line sizeRead Block (Dcache load miss refill)Read Block Shared (Icache refill)Read Block Modified (Dcache store miss refill)Change to Dirty (first store to clean block already in cache)Number of clocks CPU is active when HTC is activeNumber of clocks CPU clock is inactive when HTC is activeNumber of clocks when die temperature is higher than the software high temperature thresholdNumber of clocks when high temperature threshold was exceededNumber of correctable and Uncorrectable DRAM ECC errorsMemory controller high priority bypassMemory controller low priority bypassDRAM controller interface bypassAll Memory Controller TurnaroundsWith low op in position 0, 1, or 2Packed SSE and SSE2 instructionsScalar SSE and SSE2 instructionsX87, MMX(TM), 3DNow!(TM), Scalar and Packed SSE and SSE2 instructionsL2 fills (victims from L1 caches, TLB page table walks and data prefetches)DC fill (includes possible replays, whereas event 41h does not)DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONSData cache misses by locked instructionsLoad (Prefetch, PrefetchT0/T1/T2)Requests to non-cacheable (UC) memoryRequests to write-combining (WC) memory or WC buffer flushes to WB memoryThe number of locked instructions executedThe number of cycles spent in speculative phaseThe number of cycles spent in non-speculative phase (including cache miss penalty)Cycles in which the FPU is EmptyNumber of Cycles that a Serializing uop is in the FP SchedulerPipeline Restart Due to Self-Modifying CodePipeline Restart Due to Probe HitCANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONSCancelled Store to Load Forward OperationsData Cache Refills from L2 or NorthbridgeData Cache Refills from the NorthbridgeIneffective Software PrefetchesAverage L1 refill latency for Icache and Dcache misses (request count for cache refills)Average L1 refill latency for Icache and Dcache misses (cycles that requests spent waiting for the refills)Northbridge Read Responses by Coherency StateINSTRUCTION_CACHE_LINES_INVALIDATEDInstruction Cache Lines InvalidatedDRAM Controller Page Table OverflowsMemory Controller DRAM Command Slots MissedCPU_TO_DRAM_REQUESTS_TO_TARGET_NODECPU to DRAM Requests to Target NodeIO_TO_DRAM_REQUESTS_TO_TARGET_NODEIO to DRAM Requests to Target NodeCPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3CPU Read Command Latency to Target Node 0-3CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3CPU Read Command Requests to Target Node 0-3CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7CPU Read Command Latency to Target Node 4-7CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7CPU Read Command Requests to Target Node 4-7CPU_COMMAND_LATENCY_TO_TARGET_NODE_0_3_4_7CPU Command Latency to Target Node 0-3/4-7CPU_REQUESTS_TO_TARGET_NODE_0_3_4_7CPU Requests to Target Node 0-3/4-7HyperTransport Link 3 Transmit BandwidthL3_FILLS_CAUSED_BY_L2_EVICTIONSL3 Fills caused by L2 EvictionsRetired x87 Floating Point OperationsNON_CANCELLED_L3_READ_REQUESTSNon-cancelled L3 Read RequestsGuest page size is larger than the host page size.Host page size is larger than the guest page size.Any line state (shared, owned, exclusive, modified)Read Block Exclusive (Data cache read)Read Block Shared (Instruction cache read)Any read modes (exclusive, shared, modify)Node Group Select. 0=Nodes 0-3. 1= Nodes 4-7.Write requests sent to the DCTRead requests (including prefetch requests) sent to the DCTPrefetch requests sent to the DCTREAD_REQUESTS_WHILE_WRITES_REQUESTSRead requests sent to the DCT while writes requests are pending in the DCTGART aperture hit on access from IOGART/DEV Request hit table walk in progressGART/DEV multiple table walk in progressUpstream display refresh/ISOC readsNon-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytesNon-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORDPosted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPosted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesSzRd Byte (4 bytes) Legacy or mapped IOSzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line sizeChange-to-Dirty (first store to clean block already in cache)Number of times the HTC trip point is crossedNumber of clocks when STC trip point activeNumber of times the STC trip point is crossedNumber of clocks HTC P-state is inactive.Number of clocks HTC P-state is activeMemory controller medium priority bypassDCT0 DIMM (chip select) turnaroundDCT1 DIMM (chip select) turnaroundSSE instructions (SSE, SSE2, SSE3, and SSE4A)INVALIDATING_PROBE_NO_IN_FLIGHTInvalidating probe that did not hit any in-flight instructions.INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHTInvalidating probe that hit one or more in-flight instructions.Instruction fetches to a 4K page.Instruction fetches to a 2M page.DC fill (includes possible replays, whereas EventSelect 041h does not)Software prefetch hit in the L1.Cache line evicted was brought into the cache with by a PrefetchNTA instruction.Cache line evicted was not brought into the cache with by a PrefetchNTA instruction.Address mismatches (starting byte not the same).The number of cycles waiting for a cache hit (cache miss penalty).Number of cycles a bottom-execute uop is in the FP schedulerNumber of cycles a bottom-serializing uop is in the FP schedulerSSE bottom-executing uops retiredSSE bottom-serializing uops retiredX87 bottom-executing uops retiredX87 bottom-serializing uops retiredMerging low quadword move uopsMerging high quadword move uopsSingle precision add/subtract opsSingle precision divide/square root opsDouble precision add/subtract opsDouble precision divide/square root opsAdd pipe ops excluding load ops and SSE move opsMultiply pipe ops excluding load ops and SSE move opsStore pipe ops excluding load ops and SSE move opsAdd pipe load ops and SSE move opsMultiply pipe load ops and SSE move opsStore pipe load ops and SSE move opsData Cache Refills from the SystemNumber of data cache accesses that miss in L1 DTLB and hit in L2 DTLBNumber of data cache accesses that miss both the L1 and L2 DTLBsDRAM_CONTROLLER_PAGE_TABLE_EVENTSDRAM Controller Page Table EventsMemory Controller RBD Queue EventsSideband Signals and Special CyclesUpstream display refresh/ISOC reads.Upstream non-display refresh reads.Number of clocks MEMHOT_L is asserted.Number of times the HTC transitions from inactive to active.PROCHOT_L asserted by an external source and the assertion causes a P-state change.F2x[1,0]94[DcqBypassMax] counter reached.DCT0 read-to-write turnaround.DCT1 read-to-write turnaround.Number of stale table entry hits. (hit on a page closed too soon).PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTEDPage table idle cycle limit incremented.PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTEDPage table idle cycle limit decremented.DRAM Controller 0 Page Table EventsDRAM Controller 1 Page Table EventsD18F2x[1,0]94[DcqBypassMax] counter reached.Bank is closed due to bank conflict with an outstanding request in the RBD queue.Page table is closed due to row inactivity.SMC that did not hit any in-flight instructions.SMC that hit one or more in-flight instructions.Requests to cache-disabled (CD) memoryNumber of uops dispatched to FPU execution pipelinesNumber of x87 floating points ops that have retiredNumber of cycles that the RSQ holds retired stores. This buffer holds the stores waiting to retired as well as requests that missed the data cache and waiting on a refillNumber of data cache accesses that miss in the L1 DTLB and hit the L2 DTLB. This is a speculative eventNumber of software prefetches that do not cause an actual data cache refillNumber of L1 I-cache and D-cache misses per buffer. Average latency by combining with MAB_WAIT_CYCLES.Latency of L1 I-cache and D-cache misses per buffer. Average latency by combining with MAB_REQUESTS.RETIRED_FLOATING_POINT_INSTRUCTIONSRetired SSE/MMX/FP InstructionsNumber of page table events in the local DRAM controllerMEMORY_CONTROLLER_RBD_QUEUE_EVENTSSIDEBAND_SIGNALS_SPECIAL_SIGNALSSideband signals and special cyclesNumber of times HTC transitions from inactive to activePROCHOT_L asserted by an external source and the assertion causes a P-state changeDCQ_BYPASS_MAX counter reachedBank is closed due to bank conflict with an outstanding request in the RBD queueDCT0 number of stale table entry hits (hit on a page closed too soon)DCT0 page table idle cycle limit incrementedDCT0 page table idle cycle limit decrementedDCT0 page table is closed due to row inactivitySSE (SSE, SSE2, SSE3, MNI) instructionsIC invalidate due to an LS probeIC invalidate due to a BU probeIc attribute writes which access the L2Ic attribute writes which store into the L2SW prefetch hit in the data cacheSW prefetch hit a pending fillSW prefetch does not get a MABNumber of locked instructions executedNumber of cycles to acquire bus lockNumber of cycles to unlock line (not including cache miss)DRAM_CONTROLLER_PAGE_TABLE_OVERFLOWSMEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSEDMEMORY_CONTROLLER_BYPASS_COUNTER_SATURATIONPROBE_RESPONSES_AND_UPSTREAM_REQUESTSLINK_TRANSMIT_BANDWIDTH_LINK_0Link Transmit Bandwidth Link 0LINK_TRANSMIT_BANDWIDTH_LINK_1Link Transmit Bandwidth Link 1LINK_TRANSMIT_BANDWIDTH_LINK_2Link Transmit Bandwidth Link 2LINK_TRANSMIT_BANDWIDTH_LINK_3Link Transmit Bandwidth Link 3CPU_COMMAND_LATENCY_TO_TARGET_NODECPU Command Latency to Target NodeREAD_REQUESTS_TO_DCT_WHILE_WRITES_PENDINGTRACK_CACHE_STAT_FOR_CHGTODIRTYTrack Cache Stat for ChgToDirtyRead Sized From Local node to Node 0Write Sized From Local node to Node 0Victim Block From Local node to Node 0Read Sized From Local node to Node 1Write Sized From Local node to Node 1Victim Block From Local node to Node 1Read Sized From Local node to Node 2Write Sized From Local node to Node 2Victim Block From Local node to Node 2Read Sized From Local node to Node 3Write Sized From Local node to Node 3Victim Block From Local node to Node 3Read Sized From Local node to Node 4Write Sized From Local node to Node 4Victim Block From Local node to Node 4Read Sized From Local node to Node 5Write Sized From Local node to Node 5Victim Block From Local node to Node 5Read Sized From Local node to Node 6Write Sized From Local node to Node 6Victim Block From Local node to Node 6Read Sized From Local node to Node 7Write Sized From Local node to Node 7Victim Block From Local node to Node 7All From Local node to Node 0-3All From Local node to Node 4-7Read block From Local node to Node 4READ_BLOCK_SHARED_LOCAL_TO_NODE_4Read block shared From Local node to Node 4READ_BLOCK_MODIFIED_LOCAL_TO_NODE_4Read block modified From Local node to Node 4CHANGE_TO_DIRTY_LOCAL_TO_NODE_4Change-to-Dirty From Local node to Node 4Read block From Local node to Node 5READ_BLOCK_SHARED_LOCAL_TO_NODE_5Read block shared From Local node to Node 5READ_BLOCK_MODIFIED_LOCAL_TO_NODE_5Read block modified From Local node to Node 5CHANGE_TO_DIRTY_LOCAL_TO_NODE_5Change-to-Dirty From Local node to Node 5Read block From Local node to Node 6READ_BLOCK_SHARED_LOCAL_TO_NODE_6Read block shared From Local node to Node 6READ_BLOCK_MODIFIED_LOCAL_TO_NODE_6Read block modified From Local node to Node 6CHANGE_TO_DIRTY_LOCAL_TO_NODE_6Change-to-Dirty From Local node to Node 6Read block From Local node to Node 7READ_BLOCK_SHARED_LOCAL_TO_NODE_7Read block shared From Local node to Node 7READ_BLOCK_MODIFIED_LOCAL_TO_NODE_7Read block modified From Local node to Node 7CHANGE_TO_DIRTY_LOCAL_TO_NODE_7Change-to-Dirty From Local node to Node 7Read block From Local node to Node 0READ_BLOCK_SHARED_LOCAL_TO_NODE_0Read block shared From Local node to Node 0READ_BLOCK_MODIFIED_LOCAL_TO_NODE_0Read block modified From Local node to Node 0CHANGE_TO_DIRTY_LOCAL_TO_NODE_0Change-to-Dirty From Local node to Node 0Read block From Local node to Node 1READ_BLOCK_SHARED_LOCAL_TO_NODE_1Read block shared From Local node to Node 1READ_BLOCK_MODIFIED_LOCAL_TO_NODE_1Read block modified From Local node to Node 1CHANGE_TO_DIRTY_LOCAL_TO_NODE_1Change-to-Dirty From Local node to Node 1Read block From Local node to Node 2READ_BLOCK_SHARED_LOCAL_TO_NODE_2Read block shared From Local node to Node 2READ_BLOCK_MODIFIED_LOCAL_TO_NODE_2Read block modified From Local node to Node 2CHANGE_TO_DIRTY_LOCAL_TO_NODE_2Change-to-Dirty From Local node to Node 2Read block From Local node to Node 3READ_BLOCK_SHARED_LOCAL_TO_NODE_3Read block shared From Local node to Node 3READ_BLOCK_MODIFIED_LOCAL_TO_NODE_3Read block modified From Local node to Node 3CHANGE_TO_DIRTY_LOCAL_TO_NODE_3Change-to-Dirty From Local node to Node 3Address (including extensions) DW sentWhen links are unganged, enable this umask to select sublink 1When links are unganged, enable this umask to select sublink 0 (default when links ganged)GART_APERTURE_HIT_ON_ACCESS_FROM_CPUGART_APERTURE_HIT_ON_ACCESS_FROM_IOGART_REQUEST_HIT_TABLE_WALK_IN_PROGRESSGART Request hit table walk in progressGART_MULTIPLE_TABLE_WALK_IN_PROGRESSGART multiple table walk in progressPROBE_HIT_DIRTY_WITHOUT_MEMORY_CANCELPROBE_HIT_DIRTY_WITH_MEMORY_CANCELUPSTREAM_DISPLAY_REFRESH_ISOC_READSUPSTREAM_NON-DISPLAY_REFRESH_READSNon-Posted SzWr Byte (1-32 bytes). Typical Usage: Legacy or mapped IO, typically 1-4 bytes.Non-Posted SzWr DW (1-16 dwords). Typical Usage: Legacy or mapped IO, typically 1Posted SzWr Byte (1-32 bytes). Typical Usage: Subcache-line DMA writes, size varies; alsoPosted SzWr DW (1-16 dwords). Typical Usage: Block-oriented DMA writes, often cache-lineSzRd Byte (4 bytes). Typical Usage: Legacy or mapped IO.SzRd DW (1-16 dwords). Typical Usage: Block-oriented DMA reads, typically cache-line size.NUM_CLOCKS_HTC_PSTATE_INACTIVENumber of clocks HTC P-state is inactiveMEMORY_CONTROLLER_HIGH_PRIORITY_BYPASSMEMORY_CONTROLLER_MEDIUM_PRIORITY_BYPASSDCT0 Command Slots Missed (in MemClks)DCT1 Command Slots Missed (in MemClks)Number of Move Elimination and Scalar Op OptimizationNumber of Cycles that a Bottom-Execute uop is in the FP SchedulerCanceled Store to Load Forward OperationsDATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGEDATA_CACHE_REFILLS_FROM_NORTHBRIDGEResponse From System on Cache RefillsMicrosequencer Stall due to SerializationDISPATCH_STALL_FOR_RETIRE_QUEUE_FULLDispatch Stall for Instruction Retire Q FullDISPATCH_STALL_FOR_INT_SCHED_QUEUE_FULLDispatch Stall for Integer Scheduler Queue FullDispatch Stall for FP Scheduler Queue FullMICROSEQ_STALL_WAITING_FOR_ALL_QUIETMicrosequencer Stall Waiting for All QuietLOAD_L1_MISS_SEEN_BY_PREFETCHERLoad L1 miss seen by prefetcherSTORE_L1_MISS_SEEN_BY_PREFETCHERStore L1 miss seen by prefetcherNumber of ops tagged by IBS that retiredNumber of times an op could not be tagged by IBS because of a previous tagged op that has not retiredSSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4)Non-SMC invalidating probe that missed on in-flight instructionsNon-SMC invalidating probe that hit on in-flight instructionsSMC invalidating probe that missed on in-flight instructionsSMC invalidating probe that hit on in-flight instructionsInstruction fetches to a 4 KB pageInstruction fetches to a 2 MB pageInstruction fetches to a 1 GB pageGuest page size is larger than host page size when nested paging is enabledSplintering due to MTRRs, IORRs, APIC, TOMs or other special address regionHost page size is larger than the guest page sizeL2 Writebacks to system (Clean and Dirty)DC fill (includes possible replays, whereas PMCx041 does not)Modified (D18F0x68[ATMModeEn]==0), Modified written (D18F0x68[ATMModeEn]==1)Requests to non-cacheable (WC, but not WC+/SS) memoryRequests to non-cacheable (WC+/SS, but not WC) memorySoftware prefetch hit in the L1Software prefetch hit in the L24 KB unified TLB miss for data2 MB unified TLB miss for data1 GB unified TLB miss for data4 KB unified TLB miss for instruction2 MB unified TLB miss for instruction1 GB unified TLB miss for instruction4 KB unified TLB hit for instruction2 MB unified TLB hit for instruction1 GB unified TLB hit for instructionFill with good data. (Final valid status is valid)Early valid status turned out to be invalidFirst data cache miss or streaming store to a 64B cache lineFirst streaming store to a 64B cache lineStore is smaller than load or different starting byte but partial overlapNumber of cycles spent in non-speculative phase, excluding cache miss penaltyNumber of cycles spent in non-speculative phase, including the cache miss penaltyThe number of cycles that the load buffer is fullThe number of cycles that the store buffer is fullSSE control word mispredict traps due to mispredictionsX87 control word mispredict traps due to mispredictionsNumber of SSE Move Ops eliminatedNumber of Ops that are candidates for optimization (Z-bit set or pass)Number of Scalar ops optimizedSingle-precision add/subtract FLOPSSingle-precision multiply FLOPSSingle-precision divide/square root FLOPSSingle precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSDouble precision add/subtract FLOPSDouble precision multiply FLOPSDouble precision divide/square root FLOPSDouble precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSTotal number uops assigned to Pipe 0Total number uops assigned to Pipe 1Total number uops assigned to Pipe 2Total number uops assigned to Pipe 3Total number dual-pipe uops assigned to Pipe 0Total number dual-pipe uops assigned to Pipe 1Total number dual-pipe uops assigned to Pipe 2Total number dual-pipe uops assigned to Pipe 3AMD64 Fam17h Zen1 (deprecated - use amd_fam17h_zen1 instead)Number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB.Number of instruction fetches that miss in both the L1 and L2 TLBs.This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 and therefore requires the MergeEvent. On Linux, the kernel handles this case without the need to pass the merge event.Number of cycles when the divider is busy.Number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts.Number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction.RETIRED_INDIRECT_BRANCH_INSTRUCTIONS_MISPREDICTEDNumber of indirect branches retired there were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted condition branch instruction. Only EX mispredicts are counted.RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTEDNumber of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts).Number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts.Number of retired taken branch instructions that were mispredicted.RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONSNumber of retired conditional branch instructions.Number of uops retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8.Number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3.Number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions, it is not suitable for measuring MFLOPS.Number of near return instructions (RET or RETI) retired.Number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction.RETIRED_BRANCH_MISPREDICTED_DIRECTION_MISMATCHNumber of retired conditional branch instructions that were not correctly predicted because of branch direction mismatchNumber of 64-byte instruction cachelines that was fulfilled by the L2 cache.Number of 64-byte instruction cachelines fulfilled from system memory or another cache.CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUSL2 cache request outcomes. This event does not count accesses to the L2 cache by the L2 prefetcher.Number of L2 prefetcher hits in the L2Number of L2 prefetcher hits in the L3Number of L2 prefetcher misses in the L3Multi-events in that LS and IF requests can be received simultaneous.Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.Number of software prefetches that did not fetch data outside of the processor core.SOFTWARE_PREFETCH_DATA_CACHE_FILLSNumber of software prefetches fills by data sourceHARDWARE_PREFETCH_DATA_CACHE_FILLSNumber of hardware prefetches fills by data sourceCounts the number of retired locked instructionsCounts the number of retired non-speculative clflush instructionsCounts the number of retired cpuid instructionsCounts the number system management interrupts (SMI) receivedCounts the number of interrupts takenNumber of core cycles not in halted stateSoftware Prefetch Instructions Dispatched. This is a speculative eventNumber of STore Lad Forward hits.Number of store commit cancellationsNumber of L1 branch prediction overrides of existing prediction. This is a speculative event.Number of L2 branch prediction overrides of existing prediction. This is a speculative event.Number of indirect branch prediction for potential multi-target branch. This is a speculative event.Number of decoder overrides of existing branch prediction. This is a speculative event.Instruction fetches that hit in the L1 ITLBCycles where the uops queue is emptyNumber of uops dispatched from either the Decoder, OpCache or bothDISPATCH_RESOURCE_STALL_CYCLES_1Number of cycles where a dispatch group is valid but does not get dispatched due to a Token StallDISPATCH_RESOURCE_STALL_CYCLES_0The number of serializing Ops retired.Floating-point dispatch faultsDemand Data Cache fills by data sourceDouble precision add/subtract flops.X87 control word mispredict traps due to mispredction in RC or PC, or changes in mask bits.X87 bottom-executing uops retired.SSE control word mispreduct traps due to mispredctions in RC, FTZ or DAZ or changes in mask bits.SSE bottom-executing uops retired.Number of cycles ALU tokens total unavailable.Number of cycles stalled due to integer physical register file resource stalls. Applies to all uops that have integer destination register.Number of cycles stalled due to load queue resource stalls. Applies to all uops with load semantics.Number of cycles stalled due to store queue resource stalls. Applies to all uops with store semantics.Number of cycles stalled due to integer scheduler miscellaneous resource stalls.TAKEN_BRANCH_BUFFER_RSRC_STALLNumber of cycles stalled due to taken branch buffer resource stalls.Number of cycles stalled due to floating-point register file resource stalls.Number of cycles stalled due to floating-point scheduler resource stalls.Number of cycles stalled due to floating-point miscellaneous resource unavailable.Number of uops dispatched from the DecoderNumber of uops dispatched from the OpCacheNumber of prefetcht0, perfetcht1, prefetcht2 instructions dispatchedNumber of prefetchtw instructions dispatchedNumber of prefetchtnta instructions dispatchedData TLB reload to a 1GB page that missed in the L2 TLBData TLB reload to a 2MB page that missed in the L2 TLBTLB_RELOAD_COALESCED_PAGE_MISSData TLB reload to coalesced pages that missedData TLB reload to a 4KB page that missed in the L2 TLBData TLB reload to a 1GB page that hit in the L2 TLBData TLB reload to a 2MB page that hit in the L2 TLBData TLB reload to coalesced pages that hitData TLB reload to a 4KB page thta hit in the L2 TLBNon cacheable store and the non-cacheable commit buffer is full.Fill from another cache (home node local).Fill from DRAM (home node local).Fill from another cache (home node remote).Fill from DRAM (home node remote).Software prefetch instructions saw a match on an already allocated miss request buffer.Software Prefetch instruction saw a DC hitLoad/Store single uops dispatched (compare-and-exchange).Lock in cacheable memory region.Store-to-load conflicts. A load was unable to complete due to a non-forwardable conflict with an older store.Number of miscellaneous requests covered in more details by REQUESTS_TO_L2_GROUP2Number of data cache reads sized.Number of data cache reads sized non-cacheable.Number of instruction cache reads sized.Number of instruction cache reads sized non-cacheable.Number of self-modifying code invalidates.Number of data cache reads (including software and hardware prefetches).Number of data cache shared reads.Number of instruction cache reads.Number of requests change to writable. Check L2 for current state.Number of prefetches accepted by L2 pipeline, hit or miss.Number of miscellaneous requests covered in more details by REQUESTS_TO_L2_GROUP1Number of data cache shared read hitting in the L2.Number of data cache reads hitting in the L2.Number of data cache reads hitting a shared in line in the L2.Number of data cache store or state change (to exclusive) requests hitting in the L2.Number of data cache fill requests missing in the L2 (all types).Number of I-cache fill requests hitting a modifiable (exclusive) line in the L2.Number of I-cache fill requests hitting a clean line in the L2.Number of I-cache fill requests missing the L2.Number of times a uop could not be tagged by IBS because of a previous tagged uop that has not retired.Number of uops tagged by IBS that retired.Number of SSE instructions (SSE, SSE2, SSE3, SSE$, SSE4A, SSE41, SSE42, AVX).L1 instruction fetch that hit a 1GB page.L1 instruction fetch that hit a 2MB page.L1 instruction fetch that hit a 4KB page.Number of instruction fetches to a 1GB pageNumber of instruction fetches to a 2MB pageNumber of instruction fetches to a 4KB pageThe number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB.The number of instruction fetches that miss in both the L1 and L2 TLBs.The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event.The number of ITLB reload requests.The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts.The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction.The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts).The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare.The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts.The number of retired taken branch instructions that were mispredicted.RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS_MISPREDICTEDThe number of uops retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4.RETIRED_FUSED_BRANCH_INSTRUCTIONSThe number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3.The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS.The number of near return instructions (RET or RETI) retired.The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction.NUMBER_OF_MOVE_ELIMINATION_AND_SCALAR_OP_OPTIMIZATIONThis is a dispatch based speculative event. It is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15.RETIRED_X87_FLOATING_POINT_OPERATIONSThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8.This is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the scheduler. Invert this to count cycles in which at least one FPU operation is present in the FPU.The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. (See Core::X86::Pmc::Core::ExRetMmxFpInstr). Since this event includes non-numeric operations it is not suitable for measuring MFLOPS.The number of 64-byte instruction cachelines that was fulfilled by the L2 cache.The number of 64-byte instruction cachelines fulfilled from system memory or another cache.The number of instruction cachelines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.32_BYTE_INSTRUCTION_CACHE_FETCHThe number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses).32_BYTE_INSTRUCTION_CACHE_MISSESThe number of 32B fetch windows tried to read the L1 IC and missed in the full tag.This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher.CYCLES_WITH_FILL_PENDING_FROM_L2Total cycles spent with one or more fill requests in flight from L2.Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. This may be used to calculate average latency by multiplying this count by four and then dividing by the total number of L2 fills (umask L2RequestG1). Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event.The number of software prefetches that did not fetch data outside of the processor core.Lock operations. Unit masks ORedSoftware Prefetch Instructions Dispatched.DYNAMIC_TOKENS_DISPATCH_STALLS_CYCLES_0Cycles where a dispatch group is valid but does not get dispatched due to a token stall.Indirect Branch Prediction for potential multi-target branch (speculative)Decoder Overrides Existing Branch Prediction (speculative)Load/Store Readblock L hit eXclusive.Load/Store ReadBlock L hit Shared.Load/Store ReadblockX/ChangeToX hit eXclusive.Load/Store ReadBlock C S L X Change To X Miss.IC pipe was stalled during this clock cycle for any reason (nothing valud in pipe ICM1).IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.IC pipe was stalled during this clock cycle (ncluding IC to OC fetches) due to back pressure.IC line invalidated due to L2 invalidating probe (external or LS).IC line invalidated due to overwriting fill response.Total number of multi-pipe uops assigned to pipe3Total number of multi-pipe uops assigned to pipe2Total number of multi-pipe uops assigned to pipe1Total number of multi-pipe uops assigned to pipe0Total number of uops assigned to pipe3Total number of uops assigned to pipe2Total number of uops assigned to pipe1Total number of uops assigned to pipe0Double precision multiply-add flops.Double precision divide/square root flops.Double precision multiply flops.Single precision multiply-add flops.Single precision divide/square root flops.Single precision multiply flops.Single precision add/subtract flops.Number of scalar ops optimized.Number of ops that are candidates for optimization (have z-bit either set or pass.Number of SSE move ops eliminated.Transactions dispatched to load-store unitCommands realted to uncachable memory and I/OCommands realted to read block operationsCommands realted to change dirty operationsMiss address buffer wait cyclesL2I Responses by Coherency State16-byte transfers written to systemInternal probes causing cache lines to be invalidatedInstruction fetches that miss in 4k and 2M ITLBRetired mispredicted taken branches due to target mismatchOps tagged by IBS that retiredSSE, SSE2, SSE3, MNI instructionsRetired indirect branch instruction.Retired mispredicted near unconditional jump.Instruction cache invalidate due to LS probeInstruction cache invalidate due to BU probeModification of instructions of data too close to codeExecution of modified instruction or data too close to codeINSTRUCTION_ATTRIBUTE_EVICTIONSInstruction attribute evictionsByte enable mask for uncacheabe or I/O storeData for uncacheabe or I/O storeBYTE_ENABLE_MASK_WRITE_COMBINEByte enable mask for write combine context flushData for write combine contet flushInstruction cache miss buffer 0Instruction cache miss buffer 1Any instruction cache miss bufferRead block speculative modifiedSoftware prefetch hit in data cacheSoftware prefetch hit a pending fillSoftware prefetches that don't get a MABSoftware prefetches that hit in L2Misaligns that cross 16 Byte boundaryMisaligns that cross a 4kB boundaryThe number of cycles to acquire bus lockThe number of cycles to unlock cache lineEvictions caused by invalidating probesSSE control-renaming uops retiredX87 control-renaming uops retiredNumber of X87 floating-point ops retiredThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 and therefore requires the MergeEventThe number of serializing ops retiredThe number of retired floating-point ops by widthThe number of retired floating-point ops by typeThe number of retired integer ops (SSE/AVX)The number of packed floating-point operationsThe number of packed integer operationsCounts the number of operations dispatched to the LS unit. Unit Masks ADDedNumber of STore to Load Forward hitsCounts when a LS pipe allocates a MAB entryDEMAND_DATA_CACHE_FILLS_FROM_SYSTEMANY_DATA_CACHE_FILLS_FROM_SYSTEMAny Data Cache fills by data sourceNumber of software prefetches that did not fetch data outside of the processor coreCounts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache missesNumber of core cycle4s not in halted state by P-levelNumber of 64-byte instruction cachelines that was fulfilled by the L2 cacheNumber of 64-byte instruction cachelines fulfilled from system memory or another cacheNumber of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLBThe number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB missesNumber of L2 branch prediction overrides of existing prediction. This is a speculative eventNumber of times a branch used the indirect predictor to make a predictionNumber of decoder overrides of existing branch predictionNumber of HW resyncs (pipeline restarts) or NC redirects. NC redirects occur when front-end transitions to fetching from un-cacheable memoryCounts various IC tag related hit and miss eventsCounts op cache micro-tag hit/miss eventsNumber of cycles where the uop queue is emptyOPS_SOURCE_DISPATCHED_FROM_DECODERNumber of ops dispatched from the decoder classified by op sourceOPS_TYPE_DISPATCHED_FROM_DECODERNumber of ops dispatched from the decoder classified by op typeDISPATCH_RESOURCE_STALL_CYCLES_2For each cycle, counts the number of dispatch slots that remained unused for a given reasonNumber of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interruptsNumber of retired branch instructions, that were mispredictedNumber of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interruptsNumber of retired taken branch instructions that were mispredictedNumber of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch predictionNumber of near return instructions (RET or RET Iw) retiredNumber of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instructionNumber of indirect branches retired there were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted condition branch instruction. Only EX mispredicts are countedNumber of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions, it is not suitable for measuring MFLOPSRETIRED_INDIRECT_BRANCH_INSTRUCTIONSNumber of indirect branches retiredNumber of retired conditional branch instructionsNumber of cycles when the divider is busyCounts cycles when the hardware does not retire any ops for a given reason. Event can only track one reason at a time. If multiple reasons apply for a given cycle, the lowest numbered reason is countedNumber of microcode instructions retiredNumber of microcode ops retiredRETIRED_UNCONDITIONAL_INDIRECT_BRANCH_INSTRUCTIONS_MISPREDICTEDNumber of retired unconditional indirect branch instructions that were mispredictedRETIRED_UNCONDITIONAL_BRANCH_INSTRUCTIONSNumber of retired unconditional branch instructionsCounts retired fused instructionsL2 cache request outcomes. This event does not count accesses to the L2 cache by the L2 prefetcherNumber of L2 prefetches that hit in the L2Number of L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3Number of L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 cachesNumber of cycles when there were no valid ops in the retire queue. This may be caused by front-end bottlenecks or pipeline redirectsNumber of cycles when the oldest retire slot did not have its completion bits set. Only load and ALU completion consideredNumber of cycles when the oldest retire slot did not have its completion bits set. Only missing Load completion consideredNumber of cycles where ops could have retired but were stopped from retirement for other reasons: retire breaks, traps, faults, etcNumber of cycles where ops could have retired but did not because thread arbitration did not select the thread for retireCounts cycles dispatch is stall due to the lack of dispatch resourcesCounts dispatch slots left empty because the front-end did not supply opsCounts uops unable to dispatch due to back-end stallsCounts dispatch slots left empty because of back-end stallsCounts at P0 frequency (same as MPERF) when CPU is not in halted stateNumber of floating-point 128-bit ADD ops retiredNumber of floating-point 128-bit SUB ops retiredNumber of floating-point 128-bit MUL ops retiredNumber of floating-point 128-bit MAC ops retiredNumber of floating-point 128-bit DIV ops retiredNumber of floating-point 128-bit SQRT ops retiredNumber of floating-point 128-bit CMP ops retiredNumber of floating-point 128-bit CVT ops retiredNumber of floating-point 128-bit 256-bit BLEND ops retiredNumber of floating-point 128-bit SHUFFLE ops retiredNumber of floating-point 128-bit LOGICAL ops retiredNumber of other floating-point 128-bit ops retiredNumber of any  floating-point 128-bit ops retiredNumber of floating-point 256-bit ADD ops retiredNumber of floating-point 256-bit SUB ops retiredNumber of floating-point 256-bit MUL ops retiredNumber of floating-point 256-bit MAC ops retiredNumber of floating-point 256-bit DIV ops retiredNumber of floating-point 256-bit SQRT ops retiredNumber of floating-point 256-bit CMP ops retiredNumber of floating-point 256-bit CVT ops retiredNumber of floating-point 256-bit BLEND ops retiredNumber of floating-point 256-bit SHUFFLE ops retiredNumber of floating-point 256-bit LOGICAL ops retiredNumber of other floating-point 256-bit ops retiredAny floating-point 256-bit ops retiredNumber of integer 128-bit ADD ops retiredNumber of integer 128-bit SUB ops retiredNumber of integer 128-bit MUL ops retiredNumber of integer 256-bit MAC ops retiredNumber of integer 128-bit AES ops retiredNumber of integer 128-bit SHA ops retiredNumber of integer 128-bit CMP ops retiredNumber of integer 128-bit CLM ops retiredNumber of integer 128-bit SHIFT ops retiredNumber of integer 128-bit MOV ops retiredNumber of integer 128-bit SHUFFLE ops retiredNumber of integer 128-bit PACK ops retiredNumber of integer 128-bit LOGICAL ops retiredNumber of other integer 128-bit ops retiredAny integer 128-bit ops retiredNumber of integer 256-bit ADD ops retiredNumber of integer 256-bit SHIFT ops retiredNumber of integer 256-bit MUL ops retiredNumber of integer 256-bit CMP ops retiredNumber of integer 256-bit MOV ops retiredNumber of integer 256-bit SHUFFLE ops retiredNumber of integer 256-bit NONE ops retiredNumber of integer 256-bit LOGICAL ops retiredNumber of other integer 256-bit ops retiredAny integer 256-bit ops retiredNumber of divide and square root opsNumber of requests from the L2Stream prefetcherNumber of requests from the L2 Next Line prefetcherNumber of requests from the L2 Up Down prefetcherNumber of requests from the L2 Burst  prefetcherNumber of requests from the L2 Stride prefetcherNumber of requests from the L2 Stream prefetcherNumber of requests from the L1 Stride prefetcherNumber of requests from the L1 Region prefetcherNumber of data cache shared read hitting in the L2Number of data cache reads hitting in the L2Number of data cache reads hitting a non-modifiable line in the L2Number of data cache store or state change requests hitting in the L2Number of data cache requests missing in the L2 (all types)Number of instruction cache fill requests hitting a modifiable line in the L2Number of instruction cache fill requests hitting a non-modifiable line in the L2Number of instruction cache fill requests missing the L2Number of data cache reads (including software and hardware prefetches)Number of data cache shared readsNumber of instruction cache readsNumber of data requests change to writable, check L2 for current stateNumber of prefetches accepted by L2 pipeline, hit or missCount various non-cacheable requests: non-cached data read, non-cached instruction reads, self-modifying code checksNumber of times a op could not be tagged by IBS because of a previous tagged op that has not retiredNumber of SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)Number of cycles stalled due to no tokens available for Integer Scheduler Queue 0Number of cycles stalled due to no tokens available for Integer Scheduler Queue 1Number of cycles stalled due to no tokens available for Integer Scheduler Queue 2Number of cycles stalled due to no tokens available for Integer Scheduler Queue 3Number of cycles stalled due to insufficient tokens available for Retire QueueNumber of cycles stalled due to integer physical register file resource stalls. Applies to all ops that have integer destination registerNumber of cycles stalled due to load queue resource stallsNumber of cycles stalled due to store queue resource stallsNumber of cycles stalled due to taken branch buffer resource stallsNumber of cycles stalled due to floating-point register file resource stalls. Applies to all FP ops that have a destination registerNumber of cycles stalled due to floating-point scheduler resource stallsNumber of cycles stalled due to floating-point flush recoveryNumber of ops fetched from Instruction Cache and dispatchedNumber of ops fetched from Op Cache and dispatchedNumber of ops fetched from Loop bufferAll instruction cache accessesL1 instruction fetch TLB hit a 1GB page sizeL1 instruction fetch TLB hit a 2MB page sizeL1 instruction fetch TLB hit a 4KB or 16KB page sizeNumber of instruction fetches to a >4K coalesced pageSoftware prefetch instructions saw a match on an already allocated miss request bufferThe number of 4KB misaligned (page crossing) loadsThe number of 64B misaligned (cacheline crossing) loadsData TLB reload to a coalesced page that also missed in the L2 TLBData TLB reload to a coalesced page that hit in the L2 TLBData TLB reload to a 4KB page that hit in the L2 TLBFill from local L2 to the coreFill from L3 or different L2 in same CCXFill from cache of different CCX in same nodeFill from DRAM or IO connected to same nodeFill from CCX cache in different nodeFill from DRAM or IO connected from a different node (same socket or remote)Hardware prefetcher allocationsNon cacheable store and the non-cacheable commit buffer is fullDispatched op that performs a load from and store to the same memory addressStore-to-load conflicts. A load was unable to complete due to a non-forwardable conflict with an older storeNumber of MMX SHIFT ops retiredNumber of MMX SHUFFLE ops retiredNumber of MMX PACK ops retiredNumber of MMX LOGICAL ops retiredNumber of other MMX ops retiredNumber of SSE/AVX ADD ops retiredNumber of SSE/AVX SUB ops retiredNumber of SSE/AVX MUL ops retiredNumber of SSE/AVX MAC ops retiredNumber of SSE/AVX AES ops retiredNumber of SSE/AVX SHA ops retiredNumber of SSE/AVX CMP ops retiredNumber of SSE/AVX CLM ops retiredNumber of SSE/AVX SHIFT ops retiredNumber of SSE/AVX MOV ops retiredNumber of SSE/AVX SHUFFLE ops retiredNumber of SSE/AVX PACK ops retiredNumber of SSE/AVX LOGICAL ops retiredNumber of other SSE/AVX ops retiredNumber of scalar ADD ops retiredNumber of scalar SUB ops retiredNumber of scalar MUL ops retiredNumber of scalar MAC ops retiredNumber of scalar DIV ops retiredNumber of scalar SQRT ops retiredNumber of scalar CMP ops retiredNumber of scalar CVT ops retiredNumber of scalar BLEND ops retiredNumber of other scalar ops retiredNumber of anyscalar ops retiredNumber of vector ADD ops retiredNumber of vector SUB ops retiredNumber of vector MUL ops retiredNumber of vector MAC ops retiredNumber of vector SQRT ops retiredNumber of vector CMP ops retiredNumber of vector CVT ops retiredNumber of vector BLEND ops retiredNumber of vector SHUFFLE ops retiredNumber of vector LOGICAL ops retiredNumber of other vector ops retiredNumber of scalar ADD and vector ALL ops retiredx87 control word mispredict traps due to mispredction in RC or PC, or changes in Exception Mask bitsx87 bottom-executing ops retiredSSE/AVX control word mispredict trapsSSE/AVX bottom-executing ops retiredMultiply-Accumulate flops. Each MAC operation is counted as 2 FLOPS. This event does not include bfloat MAC operationsBfloat Multiply-Accumulate flops. Each MAC operation is counted as 2 FLOPSDouble precision add/subtract flopsThe number of serializing Ops retiredCounts cycles where the decoded uops queue is emptyNumber of requests generated by L2 hardware prefetcherNumber of requests generated by L1 hardware prefetcherNumber of requests change to writable, check L2 for current stateNumber of cycles stalled due to load queue resource stalls. Applies to all ops with load semanticsNumber of cycles stalled due to store queue resource stalls. Applies to all ops with store semanticsNumber of cycles stalled due to floating-point scheduler resource stalls. Applies to ops that use the FP schedulerAny FP dispatch. Count aligns with IBS countAny Integer dispatch. Count aligns with IBS countAny FP dispatch. Count aligns with RETIRED_OPS countAny Integer dispatch. Count aligns with RETIRED_OPS countFill from DRAM or IO connected in same nodeFill from DRAM or IO connected in different nodeMultiply-Accumulate flops. Each MAC operation is counted as 2 FLOPS[L3=0x%lx event=0x%x umask=0x%x
Number of requests to L3 cacheEach cycle, this event increments by the total number of read requests outstanding from the CCX divided by XiSysFillLatencyDivider. The user can calculate the average system fill latency in cycles by multiplying by XiSysFillLatencyDivider and dividing by the total number of fill requests over the same period (counted by event 0x9A UserMask 0x1F). XiSysFillLatencyDivider is 16 for this product, but may change for future productsSTORE_GLOBALLY_VISIBLE_CANCELS_2Count reasons why a store coalescing buffer (SCB) commit is canceledCounts events that cause a Write Combining Buffer (WCB) entry to closeCounts the in-flight L1 data cache misses each cycleNumber of core cycles not in halted state by P-levelNumber of times the Branch Predictor (BP) flushed its own pipeline due to internal conditions such as a second level prediction structure. Does not count the number of bubbles caused by these internal flushesCounts redirects of the branch predictorCounts significant Fetch Instruction Based Sampling (IBS) state transitionsNumber of cycles where the op queue is emptyNumber of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Only EX mispredicts are countedAll L2 cache requests (rare cases)Number of write combining buffer (WCB) operationsCounts requests generated from L2 hardware prefetchersCounts requests generated from L1 DC hardware prefetchersCounts requests generated from L1 DC and L2 hardware prefetchersNumber of data cache store requests hitting in the L2Number of data cache requests missing in the L2Number of instruction cache fill requests missing in the L2LS sized read, coherent non-cacheableLS sized read, non-coherent, non-cacheableNumber of times a op could not be tagged by IBS because of a previous tagged op that has not yet signaled interruptNumber of cycles when the oldest retire slot did not have its completion bits setCounts cycles dispatch is stalled due to the lack of dispatch resourcesCounts ops unable to dispatch due to back-end stallsCounts ops unable to dispatch because the dispatch cycle was granted to the other SMT threadNumber of cycles stalled due to insufficient tokens available for ALUNumber of cycles stalled due to insufficient tokens available for AgenNumber of cycles stalled due to integer execution flush recovery pendingNumber of cycles stalled due to integer physical register file resource stallsNumber of ops dispatched from x86 decoderNumber of ops dispatched from Op CacheCounts the number of valid fetch IBS samples that were collected. Each valid sample also created an IBS interruptCounts the number of fetch IBS tagged fetches that were discarded due to IBS filtering. When a tagged fetch is discarded the fetch IBS facility will automatically tag a new fetchCounts when the fetch IBS facility discards an IBS tagged fetch for reasons other than IBS filtering. When a tagged fetch is discarded the fetch IBS facility will automatically tag a new fetchCounts the number of fetches tagged for fetch IBS. Not all tagged fetches create an IBS interrupt and valid fetch sampleMispredict redirect from EX (execution-time)Resync redirect from RT (retire-time)All 64 bytes of the WCB entry have been writtenOlder SCB being waited on to become globally visible was unable to become globally visibleNumber of non-cacheable or cacheline-misaligned locksNumber of integer 128-bit CVT or PACK ops retiredNumber of integer 128-bit VNNI ops retiredNumber of integer 256-bit AES ops retiredNumber of integer 256-bit SHA ops retiredNumber of integer 256-bit CVT or PACK ops retiredNumber of integer 256-bit VNNI ops retiredNumber of floating-point 128-bit MOV ops retiredNumber of floating-point 128-bit BFloat ops retiredNumber of floating-point 256-bit MOV ops retiredNumber of floating-point 256-bit BFloat ops retiredNumber of MMX CVT or PACK ops retiredNumber of MMX VNNI ops retiredNumber of SSE/AVX CVT or PACK ops retiredNumber of SSE/AVX VNNI ops retiredNumber of scalar MOV ops retiredNumber of scalar SHUFFLE ops retiredNumber of scalar BFloat ops retiredNumber of scalar LOGICAL ops retiredNumber of any scalar ops retiredNumber of vector MOV ops retiredNumber of vector BFloat ops retiredpfmlib_validate_encodingpfmlib_parse_event_attrpfmlib_build_event_pattrspfmlib_parse_eventpfmlib_pmu_activatepfmlib_pmu_sanity_checkspfmlib_init_pmuspfmlib_init_ospfmlib_check_structpfmlib_raw_pmu_encodepfm_perf_pmu_supported_plmperf_table_alloc_eventadd_optional_eventspfm_perf_get_encodingpfm_perf_add_defaultspfm_perf_get_perf_encoding����h��8��������@������ʲ��\��\��D���b��(����D��pfmlib_check_no_modspfmlib_perf_event_encodepfmlib_perf_find_pmu_typepfm_perf_find_pmu_typepfm_init_sysfs_pmu_cachepfm_intel_x86_get_perf_encodingpfm_amd64_get_perf_encoding@�����������������������P������������������p��`��.��Q����������������$��$��$���������h��H��������l��L��,������$����amd64_add_defaultspfm_amd64_get_encoding�������P�������0���������d��M��6���������������{��pfm_intel_x86_get_event_infopfm_intel_x86_get_event_attr_infointel_x86_check_max_grpidpfm_intel_x86_encode_genpfm_intel_x86_add_defaultscreate_arch_event_table&'56pfm_nhm_unc_get_encoding,/.,/%-**>:?<EFOV=GUN^����jl}~��������u&� &��%�%� %�$�p$�($�#�#�P#� #�"�P"��!�0 �!�0 �!�@!�!� �` ��&�+�o+�D+�,+�+�*��*�*�`*�?*�"*�*��)��)�)�)�})�a)�H)�/)�)�(�(�W+�pfm_intel_snbep_unc_get_encodingsnbep_unc_add_defaults7ML���W�����\_�W�LX�W�T�X�;���Z�]�8�]�PH^�l�_���_���_��_��`�(8c��h�	�i� 	�j�l	�k�	l��	�l��	Hm�0
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